Proceedings ArticleDOI
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
Siddarth A. Krishnan,Unoh Kwon,Naim Moumen,Matthew W. Stoker,Eric C. Harley,Stephen W. Bedell,Deleep R. Nair,B. Greene,William K. Henson,Murshed M. Chowdhury,D.P. Prakash,Ernest Y. Wu,Dimitris P. Ioannou,Eduard A. Cartier,Myung-Hee Na,S. Inumiya,Kevin McStay,Lisa F. Edge,Ryosuke Iijima,Jin Cai,Martin M. Frank,M. Hargrove,Dechao Guo,Andreas Kerber,Hemanth Jagannathan,Takashi Ando,Joseph F. Shepard,Shahab Siddiqui,Min Dai,Huiming Bu,J. Schaeffer,Jaeger Daniel,Kathy Barla,Thomas A. Wallner,S. Uchimura,Y. Lee,Gauri Karve,Sufi Zafar,Dominic J. Schepis,Yun-Yu Wang,Ricardo A. Donaton,S. Saroop,P. Montanini,Yue Liang,James H. Stathis,Richard Carter,Rohit Pal,Vamsi Paruchuri,H. Yamasaki,J-H Lee,Martin Ostermayr,J.-P. Han,Yue Hu,Michael A. Gribelyuk,Dae-Gyu Park,X. Chen,Srikanth Samavedam,Shreesh Narasimha,Paul D. Agnello,Mukesh Khare,R. Divakaruni,Vijay Narayanan,Michael P. Chudzik +62 more
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TLDR
In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.Abstract:
Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.read more
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Journal ArticleDOI
Considerations for Ultimate CMOS Scaling
TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Proceedings ArticleDOI
22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications
Rick Carter,J. Mazurier,L. Pirro,J-U. Sachse,Peter Baars,Jürgen Faul,Carsten Grass,G. Grasshoff,Peter Javorka,Thorsten Kammler,A. Preusse,S. Nielsen,T. Heller,J. Schmidt,Heimanu Niebojewski,P-Y. Chou,Elliot John Smith,Elke Erben,C. Metze,C. Bao,Yogadissen Andee,I. Aydin,S. Morvan,J. Bernard,E. Bourjot,Thomas Feudel,David Harame,R. Nelluri,Hans-Jürgen Thees,L. M-Meskamp,J. Kluth,R. Mulfinger,Mahbub Rashed,R. Taylor,C. Weintraub,Jan Hoentschel,Maud Vinet,Jamie Schaeffer,B. Rice +38 more
TL;DR: 22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications and achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks.
Journal ArticleDOI
SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI
Jacopo Franco,B. Kaczer,Philippe Roussel,Jerome Mitard,Moonju Cho,Liesbeth Witters,Tibor Grasser,Guido Groeseneken +7 more
TL;DR: In this article, the negative bias temperature instability (NBTI) reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters was investigated.
Patent
Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology
TL;DR: In this paper, a gate structure is formed over the logic portion comprising a high k dielectric and a metal gate, which is then removed from the logic part leaving a portion of the second layer over the control gate and the select gate.
Patent
Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate
TL;DR: In this article, a process integration for fabricating nonvolatile memory (NVM) cells having recessed control gates on a first substrate area, which are encapsulated in one or more planar dielectric layers, prior to forming in-laid high-k metal select gates and CMOS transistor gates in first and second substrate areas.
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Proceedings ArticleDOI
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
X. Chen,S. Samavedam,Vijay Narayanan,Kenneth J. Stein,C. Hobbs,Christopher V. Baiocco,Weipeng Li,Jaeger Daniel,M. Zaleski,Haining Yang,Nam-Sung Kim,Yi-Wei Lee,Da Zhang,Laegu Kang,J. Chen,Haoren Zhuang,Arifuzzaman (Arif) Sheikh,J. Wallner,Michael V. Aquilino,Jin-Ping Han,Zhenrong Jin,James Chingwei Li,G. Massey,S. Kalpat,Rashmi Jha,Naim Moumen,R. Mo,S. Kirshnan,X. Wang,Michael P. Chudzik,M. Chowdhury,Deleep R. Nair,C. Reddy,Young Way Teh,Chandrasekharan Kothandaraman,Douglas D. Coolbaugh,Shesh Mani Pandey,D. Tekleab,Aaron Thean,Melanie J. Sherony,Craig S. Lage,J. Sudijono,R. Lindsay,JiYeon Ku,Mukesh Khare,An L. Steegen +45 more
TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.
Journal ArticleDOI
Diffusion versus oxidation rates in silicon‐germanium alloys
TL;DR: In this article, the authors studied the oxidation of SiGe alloys of different compositions (between 25 and 75 at.% Ge) and found that after extended oxidation, the decrease of Si concentration at the interface slowed down oxidation rates enough so that eventually, the oxide thickness for the SiGeAlloys ends up smaller than that of pure Si.
Proceedings ArticleDOI
Band-Engineered Low PMOS V T with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme
H.R. Harris,Pankaj Kalra,Prashant Majhi,Muhammad Mustafa Hussain,D. Q. Kelly,Jungwoo Oh,D. He,Casey Smith,Joel Barnett,Paul Kirsch,G. Gebara,Jesse S. Jur,Daniel J. Lichtenwalner,A. Lubow,Tso-Ping Ma,Guangyu Sung,Scott E. Thompson,Byoung Hun Lee,Hsing-Huang Tseng,Rajarao Jammy +19 more
TL;DR: In this paper, a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.
Proceedings ArticleDOI
8Å T inv gate-first dual channel technology achieving low-V t high performance CMOS
Liesbeth Witters,Shinji Takeoka,S. Yamaguchi,Andriy Hikavyy,Denis Shamiryan,Moonju Cho,Thomas Chiarella,L.-A. Ragnarsson,Roger Loo,Christoph Kerner,Y. Crabbe,J. Franco,J. Tseng,Wei-E Wang,E. Rohr,Tom Schram,O. Richard,Hugo Bender,Serge Biesemans,Philippe Absil,T. Y. Hoffmann +20 more
TL;DR: In this article, a gate-first dual Si/SiGe channel low-complexity integration approach was proposed for low V t (V t,Lg=1µm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ∼8A using a gate first dual Si and SiGe channel integration approach.
Journal ArticleDOI
Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics
David C. Gilmer,James K. Schaeffer,W.J. Taylor,C. Capasso,K. Junker,J. Hildreth,D. Tekleab,Brian A. Winstead,S. Samavedam +8 more
TL;DR: In this article, the tradeoffs in using different combinations of thin-strained Si 1 - x Gex channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high-k dielectrics in a gate-first integration technology were explored.