A model to study the effect of selective anodic oxidation on ultrathin gate oxides
TL;DR: In this paper, the effect of selective anodic oxidation on ultrathin (22-31 /spl Aring/) silicon dioxide grown at different temperatures ranging from 600/spl deg/C to 875/spl Deg/C, on both p-and n-type substrates was studied.
Abstract: We have studied the effect of selective anodic oxidation on ultrathin (22-31 /spl Aring/) silicon dioxide grown at different temperatures ranging from 600/spl deg/C to 875/spl deg/C, on both p- and n-type substrates. A model based on the concept of filling of pinholes by selective anodic oxidation is presented to quantitatively explain the reduction in the gate leakage current of the MOS capacitors after selective anodic oxidation.
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TL;DR: In this paper, anodic oxidation in 0.1 M HCl followed by a post-rapid thermal annealing process has been used to repair defects existing in thin thermally grown oxide layers (3 and 6) on a p-type silicon substrate.
18 citations
TL;DR: In this paper, negative capacitance was observed in a MOS capacitor grown on an n-type substrate with ultrathin gate oxide film, and it was found that the NC effect turned on at the flatband voltage and was mainly attributed to local electron-hole recombination occurring at the nonuniform interface.
Abstract: Negative capacitance (NC) was observed in a MOS capacitor grown on an n-type substrate with ultrathin gate oxide film. The NC effect was studied by considering the oxide thickness, the lateral nonuniformity of oxide layers, the current conduction mechanism, and the minority carrier response. It was found that the NC effect turned on at the flatband voltage and was mainly attributed to local electron-hole recombination occurring at the nonuniform interface. A circuit model including an inductive pathway is proposed to take the local electron-hole recombination into account, and the estimation of the NC response on frequency approximates the experimental observation. Because the device sizes are scaled down continuously, it is important to gain an insight into the NC phenomenon induced from the nonuniform factors in fundamental MOS devices.
11 citations
Cites background from "A model to study the effect of sele..."
...Considering the lower oxidation temperature in N1, it is inferred that the thinner EOT, the more Dit, or the more oxide nonuniformity [9] might be the reasons that the gate capacitance is more negative....
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...n-type substrates [9], [10], denoted as MOS(p)s and MOS(n)s, respectively, it was found that the fraction of pinholes in oxide...
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TL;DR: In this article, a model regarding the oxide voltage dropping efficiency with the consideration of interface trap density and effective charge number density was proposed for the observation of clear current kinked points.
Abstract: A clear current kinked phenomenon was observed in Al/SiO2/Si(p) structures with nanoscale (<2.5 nm) SiO2 in a forward biased region. It was found that the kinked points are dependent on oxide thickness and are not the same as flat-band voltages. A model regarding the oxide voltage dropping efficiency with the consideration of interface trap density (\(D_{\mathrm{it}}\)) and effective charge number density (\(Q_{\mathrm{eff}}/q\)) was proposed for the observation. It is noted that the kinked point is severely affected by the oxide quality and uniformity. However, Al/SiO2/Si(n) structures in a forward biased region do not exhibit this current kinked phenomenon because the dropping behavior of oxide is absolutely different from Al/SiO2/Si(p) structures.
11 citations
TL;DR: In this paper, the authors correlated the electrical characteristics of ultrathin gate oxide with the presence of pinholes by C-AFM studies and showed that the improvement in the gate leakage current in thermally grown oxide is indeed due to the filling of pinhole by selective anodic oxidation.
10 citations
TL;DR: In this paper, the negative capacitance effect in back-to-back combination of a metal-insulator-semiconductor (MIS) structure and a metal semiconductor junction, which is fabricated on an n type Silicon-on-Insulator substrate is reported.
Abstract: We report a strong negative capacitance effect in back to back combination of a metal-insulator-semiconductor (MIS) structure and a metal-semiconductor junction, which is fabricated on an n type Silicon-on-Insulator substrate. The MIS capacitor comprises a SiO2-HfO2 insulator stack with embedded Pt nanoparticles. The capacitor undergoes a voltage stress process and thereby turns into a varactor and a photodetector. The negative capacitance is observed only under illumination in structures that employ a Schottky back contact. A symmetric double or an asymmetric single negative capacitance peak is observed depending on the nature of illumination. The phenomenon is attributed to the modulation of the semiconductor conductance due to photo generated carriers and their incorporation in trapping/de-trapping processes on interfacial and post filamentation induced defects in the insulator stack. The frequency range of the observed effect is limited to 100 kHz. Large ratios of light to dark and maximum to minimum ...
9 citations
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67 citations
"A model to study the effect of sele..." refers background in this paper
...With lower growth temperature it is possible to obtain better control over the thickness of silicon dioxide [1], [2] but at the cost ofmore number of pinholes and defects in the oxide, resulting in increased leakage and unreliable performance [3]....
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TL;DR: In this paper, the authors show that the effective tunnel mass of SiO2 employed as a fitting parameter in standard transfer-matrix multiple-scattering theory calculations increases strongly as the oxide thickness is decreased.
Abstract: Based on the results of three-dimensional atomistic tight-binding calculations, we argue that the effective tunnel mass of SiO2 employed as a fitting parameter in standard transfer-matrix multiple-scattering theory calculations increases strongly as the oxide thickness is decreased (we find more than 50% mass enhancement upon reduction of the oxide thickness from 4 to 1 nm). At least five factors, usually neglected in effective-mass-based calculations can contribute to this effect: the nonparabolicity of the complex bands in the gap of SiO2, the gradual (rather than abrupt) change of the electrostatic potential across the Si/SiO2 interface, a possible image force correction, the presence of native defects in the oxide, and the effective-mass approximation itself. Very good quantitative agreement between the theoretical predictions for the thickness dependence of the mass enhancement and corresponding results from transfer matrix fits to experimental currents is obtained if defect densities smaller than 10...
61 citations
TL;DR: In this article, anodic oxidation at room temperature with pure deionized water as electrolyte and then followed by high-temperature rapid thermal densification was used to prepare high breakdown endurance thin-gate oxides with thicknesses of about 50 /spl Aring.
Abstract: Anodic oxidation at room temperature with pure deionized water as electrolyte and then followed by high-temperature rapid thermal densification was used to prepare high breakdown endurance thin-gate oxides with thicknesses of about 50 /spl Aring/. It was observed that the oxides prepared by anodic oxidation followed by rapid thermal densification (AOD) show better electrical characteristics than those grown by rapid thermal oxidation (RTO) only. The AOD oxides have a very low midgap interface trap density, Ditm, of smaller than 1/spl times/10/sup 10/ eV/sup -1/ cm/sup -2/ and negative effective oxide trapped charge. From the smaller leakage currents observed during staircase ramp voltage time-zero dielectric breakdown (TZDB) and constant field time-dependent dielectric breakdown (TDDB) testings, it is supposed that the uniform interfacial property and the pretrapped negative charges in AOD oxides are responsible for the improved characteristics.
26 citations
"A model to study the effect of sele..." refers background in this paper
...The improvement in gate leakage current after selective anodic oxidation is attributed to the repairing of weak spots andpinholes in theoxidebygrowinganoxideonlyover these regions due to the self-adjusting nature of anodization current through theseweakspots [6]....
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TL;DR: In this paper, a novel and simple method to determine deep ultrathin oxide thickness by measuring the MOS capacitance under the flat-band condition is reported, and the results determined by this method show good agreement with those using capacitance-voltage (C-V) simulation, ellipsometer, and high-resolution transmission electromicroscopy (HRTM) analysis for thin oxides (2/spl sim/3 nm).
Abstract: In this letter, a novel and simple method to determine deep ultrathin oxide thickness by measuring the MOS capacitance under the flat-band condition is reported. The mechanism of this method has been profoundly studied. The results determined by this method show good agreement with those using capacitance-voltage (C-V) simulation, ellipsometer, and high-resolution transmission electromicroscopy (HRTM) analysis for thin oxides (2/spl sim/3 nm). The thickness of pure oxide extracted by this method in this experiment can be down to 1.4 nm despite the obvious C-V distortion.
25 citations
"A model to study the effect of sele..." refers methods in this paper
...The gate oxide thickness has been calculated from the accumulation capacitance by amethod proposed for ultrathin oxide [5]....
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TL;DR: In this paper, the authors proposed a method to identify the weak spots in thermally grown gate oxide and repair them by selective anodization by controlling the applied voltage, ensuring that current flows only through weak spots.
Abstract: The presence of weak spots and pinholes in ultrathin gate oxides significantly increases the leakage current, thereby degrading the device performance This paper proposes a method, which identifies the weak spots in thermally grown gate oxide and repairs them by selective anodization By controlling the applied voltage, it is ensured that current flows only through the weak spots in the oxide during anodization Anodic oxide therefore grows over these weak spots, improving the reliability of the oxide without increasing the gate oxide thickness Significant improvement in electrical characteristics was observed in the gate oxides treated by anodic oxidation
18 citations
"A model to study the effect of sele..." refers background in this paper
...We have shown earlier that by using selective anodic oxidation, it is possible to repair theweak spots in the oxide, thereby improving the electrical characteristics of oxide grown on p-type substrate [4]....
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