A modified bias scheme for high-gain low-noise folded cascode OTAs
01 Oct 2017-pp 1-4
TL;DR: A modified biasing scheme for folded cascode OTAs is proposed to de-couple the gain versus noise/UGB trade-off and is illustrated with the aid of an ultra-low noise OTA design.
Abstract: Achieving large low-frequency gain together with low noise and a high unity-gain bandwidth (UGB) imposes conflicting requirement on bias currents in single stage operational transconductance amplifiers (OTA). In this work, we propose a modified biasing scheme for folded cascode OTAs to de-couple the gain versus noise/UGB trade-off. The effectiveness of proposed biasing scheme is illustrated with the aid of an ultra-low noise OTA design achieving 350 pV / √Hz along with 70 dB DC gain in 130nm CMOS process while consuming roughly half the bias current as compared to conventional biasing scheme.
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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.
1,038 citations
TL;DR: A bulk-driven, buffer-biased, gain-boosted amplifier for biomedical signal is designed using 90 nm CMOS technology to capture signal activity.
Abstract: The growing consciousness in health, biomedical research area is becoming most sought-after to develop or design medical devices by bringing biomedical researchers and clinicians to solve m...
2 citations
Cites background from "A modified bias scheme for high-gai..."
...An offset voltage is established between the input signal terminals of trans-conductance amplifier by the negative feedback which avenues the current beck into the input terminal (Agrawal & Sankaran, 2017) branch....
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References
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Book•
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents
1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging
4,826 citations
Book•
01 Jan 1987
TL;DR: In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.
Abstract: 1.1 ANALOG INTEGRATED CIRCUIT DESIGN 1.2 NOTATION, SYMBOLOGY AND TERMINOLOGY 1.3 ANALOG SIGNAL PROCESSING 1.4 EXAMPLE OF ANALOG VLSI MIXED-SIGNAL CIRCUIT DESIGN 2.1 BASIC MOS SEMICONDUCTOR FABRICATION PROCESSES 2.2 THE PN JUNCTION 2.3 THE MOS TRANSISTOR 2.4 PASSIVE COMPONENTS 2.5 OTHER CONSIDERATIONS OF CMOS TECHNOLOGY 3.1 SIMPLE MOS LARGE-SIGNAL MODEL (SPICE LEVEL 1) 3.2 OTHER MOS LARGE-SIGNAL MODEL PARAMETERS 3.3 SMALL-SIGNAL MODEL FOR THE MOS TRANSISTOR 3.4 COMPUTER SIMULATION MODELS 3.5 SUBTHRESHOLD MOS MODEL 3.6 SPICE SIMULATION OF MOS CIRCUITS 4.1 MOS SWITCH 4.2 MOS DIODE/ACTIVE RESISTOR 4.3 CURRENT SINKS AND SOURCES 4.4 CURRENT MIRRORS 4.5 CURRENT AND VOLTAGE REFERENCES 4.6 BANDGAP REFERENCE 5.1 INVERTERS 5.2 DIFFERENTIAL AMPLIFIERS 5.3 CASCODE AMPLIFIERS 5.4* CURRENT AMPLIFIERS 5.5* OUTPUT AMPLIFIERS/BUFFERS 6.1 DESIGN OF CMOS OP AMPS 6.2 COMPENSATION OF OP AMP 6.3 DESIGN OF TWO-STAGE OP AMPS 6.4 POWER-SUPPLY REJECTION RATIO OF TWO-STAGE OP AMPS 6.5 CASCODE OP AMPS 6.6 SIMULATION AND MEASUREMENT OF OP AMPS 6.7 MACROMODELS FOR OP AMPS 7.1 BUFFERED OP AMPS 7.2 HIGH-SPEED/FREQUENCY OP AMPS 7.3 DIFFERENTIAL-OUTPUT OP AMPS 7.4 MICROPOWER OP AMPS 7.5 LOW NOISE OP AMPS 7.6 LOW VOLTAGE OP AMPS 8.1 CHARACTERIZATION OF A COMPARATOR 8.2 TWO-STAGE, OPEN-LOOP COMPARATOR DESIGN 8.3 OTHER OPEN-LOOP COMPARATORS 8.4 IMPROVING THE PERFORMANCE OF OPEN-LOOP COMPARATORS 8.5 DISCRETE-TIME COMPARATORS 8.6 HIGH-SPEED COMPARATORS APPENDIX A CIRCUIT ANALYSIS FOR ANALOG CIRCUIT DESIGN APPENDIX B INTEGRATED CIRCUIT LAYOUT APPENDIX C CMOS DEVICE CHARACTERIZATION APPENDIX D TIME AND FREQUENCY DOMAIN RELATIONSHIP FOR SECOND-ORDER SYSTEMS
2,741 citations
"A modified bias scheme for high-gai..." refers background in this paper
...In the literature, a commonly suggested choice for the cascode branch current is I1 = I0/2, so as to obtain an optimal slew rate for a given bias current in the input stage [3], [4], [5]....
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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.
1,038 citations
"A modified bias scheme for high-gai..." refers background in this paper
...2(c) can be used at the expense of increased power consumption, noise and offset [3]....
[...]
...In the literature, a commonly suggested choice for the cascode branch current is I1 = I0/2, so as to obtain an optimal slew rate for a given bias current in the input stage [3], [4], [5]....
[...]
29 May 2009
TL;DR: In this article, an LNA-less mixer-first receiver is proposed, which achieves a remarkably high spurious-free dynamic range (SFDR) of 79dB in 1MHz bandwidth over a decade of RF frequencies.
Abstract: Spurious-free dynamic range (SFDR) is a key specification of radio receivers and spectrum analyzers, characterizing the maximum distance between signal and noise+distortion. SFDR is limited by the linearity (intercept point IIP3 mostly, sometimes IIP2) and the noise floor. As receivers already have low noise figure (NF) there is more room for improving the SFDR by increasing the linearity. As there is a strong relation between distortion and voltage swing, it is challenging to maintain or even improve linearity intercept points in future CMOS processes with lower supply voltages. Circuits can be linearized with feedback but loop gain at RF is limited [1]. Moreover, after LNA gain, mixer linearity becomes even tougher. If the amplification is postponed to IF, much more loop gain is available to linearize the amplifier. This paper proposes such an LNA-less mixer-first receiver. By careful analysis and optimization of a passive mixer core [2,3] for low conversion loss and low noise folding it is shown that it is possible to realize IIP3≫11dBm and NF≪6.5dB, i.e. a remarkably high SFDR≫79dB in 1MHz bandwidth over a decade of RF frequencies.
171 citations
TL;DR: In this paper, a single-channel full-duplex receiver with tunable self-interference cancellation capability through LO phase shifting is presented, which takes advantage of high linearity of the passive mixer-first architecture.
Abstract: This letter presents a single-channel full-duplex receiver with tunable self-interference (SI) cancelling capability through LO phase shifting. The receiver takes advantage of high linearity of the passive mixer-first architecture to eliminate SI without degrading sensitivity due to inter-modulation distortion. The proposed receiver exhibits a DSB noise figure of 8.6–12.5 dB over an operating frequency range of 800 MHz–1.7 GHz. It achieves >70.5 dB SINDR in 16.25 MHz RF signal bandwidth at −18 dBm input SI power. The receiver is implemented in a 130 nm CMOS process and occupies an area of 0.63 mm2.
10 citations
"A modified bias scheme for high-gai..." refers background or methods in this paper
...Negative feedback arrangement in which the designed OTA is used [2] ....
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...Figure 1(a) shows a simplified schematic of such a receiver presented in [1] and [2]....
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...For an OTA to be used in a low-noise mixer-first receiver such as [2], the baseband signal bandwidth of interest and input currents are of the order of several MHz and several mA respectively, to meet the stringent noise requirement....
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...CIRCUIT IMPLEMENTATION AND SIMULATION RESULTS To demonstrate the effectiveness of the proposed biasing scheme, a folded-cascode OTA is designed in a 130 nm CMOS process, targetting application in the mixer-first receiver presented in [2]....
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