A multiple modulator fractional divider
23 May 1990-pp 559-568
TL;DR: In this article, a CMOS integrated fractional-N divider is presented, which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier.
Abstract: Based on oversampling A/D conversion technology which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier, a CMOS integrated fractional-N divider is presented. A complete fractional-N phase locked loop (PLL) which was constructed utilizing only the CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator is discussed. The resulting PLL is shown to exhibit no fractional spurs. >
Citations
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TL;DR: A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth and indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.
Abstract: A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-/spl mu/m CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH /spl Sigma/-/spl Delta/ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.
434 citations
Cites background from "A multiple modulator fractional div..."
...If the order of is increased to the resulting signal swings will be amplified according to The achievable data rates using compensation are limited by the ability of the PLL to accommodate this increased signal swing....
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28 Oct 2010
TL;DR: A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed, using a fractional- synthesizer as the F MCW generator and millimeter-wave PA and LNA incorporated on chip, providing sufficient gain, bandwidth, and sensitivity.
Abstract: A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing a fractional- synthesizer as the FMCW generator, the transmitter linearly modulates the carrier frequency across a range of 700 MHz. The receiver together with an external baseband processor detects the distance and relative speed by conducting an FFT-based algorithm. Millimeter-wave PA and LNA are incorporated on chip, providing sufficient gain, bandwidth, and sensitivity. Fabricated in 65-nm CMOS technology, this prototype provides a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2-V supply.
397 citations
TL;DR: In this paper, a general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations, and the model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers.
Abstract: A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom /spl Sigma/-/spl Delta/ synthesizer implemented in a 0.6 /spl mu/m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.
312 citations
Cites methods from "A multiple modulator fractional div..."
...One such technique is the use of – modulation to achieve high-resolution frequency synthesizers that have relatively fast settling times, as described by Rileyet al. in [1], Copeland in [2], and Miller and Conley in [3], [4]....
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01 Jan 1998
TL;DR: In this article, a 4/sup th/order type-2 charge-pump PLL frequency synthesizer for the DCS-1800 system in a standard 0.4 /spl mu/m CMOS process without external components is presented.
Abstract: This design integrates a 4/sup th/ order type-2 charge-pump PLL frequency synthesizer for the DCS-1800 system in a standard 0.4 /spl mu/m CMOS process without external components. The VCO uses an integrated hollow planar inductor, formed in the 2 metal levels available on a lowly-doped substrate. The coil has a symmetrical octagonal shape and size optimized using 2-D circular finite-element analysis. Skin effect and eddy current losses are minimized, and the quality factor is 8.6. VCO phase noise is -122.5 dBc/Hz at 600 kHz offset and tuning range is 20%.
264 citations
Cites background from "A multiple modulator fractional div..."
...Of course, addition of the fractional- division technique is necessary to achieve a 200-kHz frequency resolution [13], [14]....
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TL;DR: In this paper, a phase noise cancellation technique and a charge pump linearization technique are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL).
Abstract: A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.
258 citations
References
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TL;DR: A modulator that employs double integration and two-level quantization is easy to implement and is tolerant of parameter variation.
Abstract: Sigma delta modulation is viewed as a technique that employs integration and feedback to move quantization noise out of baseband. This technique may be iterated by placing feedback loop around feedback loop, but when three or more loops are used the circuit can latch into undesirable overloading modes. In the desired mode, a simple linear theory gives a good description of the modulation even when the quantization has only two levels. A modulator that employs double integration and two-level quantization is easy to implement and is tolerant of parameter variation. At sampling rates of 1 MHz it provides resolution equivalent to 16 bit PCM for voiceband signals. Digital filters that are suitable for converting the modulation to PCM are also described.
608 citations
01 Dec 1987
TL;DR: A highly stable triple-integration noise-shaping technology which permits greater accuracy for monolithic audio A/D converters is discussed and a 16-bit 24-kHz bandwidth A-D converter LSI with digital filters was successfully fabricated in 2-/spl mu/m CMOS technology.
Abstract: A highly stable triple-integration noise-shaping technology which permits greater accuracy for monolithic audio A/D converters is discussed. Based on this technology, a 16-bit 24-kHz bandwidth A-D converter LSI with digital filters was successfully fabricated in 2-/spl mu/m CMOS technology. An SNR (S/(N+THD)) of 91 dB and a total harmonic distortion (THD) of 0.002% at full-scale input were attained.
394 citations
TL;DR: This paper rigorously derive several basic properties of a simple discrete-time single integrator loop sigma-delta modulator with an accumulate-and-dump demodulator and shows that when the input is constant, the state sequence of the integrator in the encoder loop can be modeled exactly as a linear system in an appropriate space.
Abstract: Oversampled sigma-delta modulation has been proposed as a practical implementation for high rate analog-to-digital conversion because of its simplicity and its robustness against circuit imperfections. To date, mathematical developments of the basic properties of such systems have been based either on simplified continuous-time approximate models or on linearized discrete-time models where the quantizer is replaced by an additive white uniform noise source. In this paper, we rigorously derive several basic properties of a simple discrete-time single integrator loop sigma-delta modulator with an accumulate-and-dump demodulator. The derivation does not require any assumptions on the correlation or distribution of the quantizer error, and hence involves no linearization of the nonlinear system, but it does show that when the input is constant, the state sequence of the integrator in the encoder loop can be modeled exactly as a linear system in an appropriate space. Two basic properties are developed: 1) the behavior of the sigma-delta quantizer when driven by a constant input and its relation to uniform quantization, and 2) the rate-distortion tradeoffs between the oversampling ratio and the average mean-squared quantization error.
373 citations
Book•
01 Jan 1981
TL;DR: The Elementary Phase-Locked Synthesizer, Modulation, Sidebands and Noise Spectrums, and its Applications: Large-Signal Performance, Natural Acquisition.
Abstract: The Elementary Phase-Locked Synthesizer. Modulation, Sidebands and Noise Spectrums. Frequency Dividers. Phase Detectors. Higher Order Loops. Sampling Effects. Architectures. Large-Signal Performance, Natural Acquisition. Acquisition Aids. Spectral Purity. Computer Aided Engineering. References. Answers to Problems. Cross-Reference from First Edition. Index.
295 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations