A Multiple-Ring-Modulated JTE Technique for 4H-SiC Power Device With Improved JTE-Dose Window
TL;DR: In this article, a multiple-ring-modulated junction termination extension (MRM-JTE) technology for large-area silicon carbide PiN rectifier rated at 4500 V is proposed and experimentally investigated using a standard two-zone JTE (TZ-jTE) process without extra process steps or masks.
Abstract: In this paper, a multiple-ring-modulated junction termination extension (MRM-JTE) technology for large-area silicon carbide PiN rectifier rated at 4500 V is proposed and experimentally investigated using a standard two-zone JTE (TZ-JTE) process without extra process steps or masks. Multiple modulation rings embedded inside JTE region, which is similar to varied lateral doping technology widely used in silicon devices, form a gradual decrease of effective charges in the termination region. MRM combines the advantages of two termination techniques, namely, ring-assisted JTE and space-modulated JTE, to enlarge the optimum JTE-dose window with high reverse blocking voltage in comparison with conventional TZ-JTE. A breakdown voltage of 4940 V at a leakage current of $1~\mu \text{A}$ is achieved from fabricated MRM-JTE rectifiers with a 36- $\mu \text{m}$ -thick N− epilayer doped to ${1.8} \times {10}^{{15}}$ cm−3, which is 92% of the ideal parallel-plane value. A forward current of 50 A has been measured at a forward voltage drop of 3.9 V for devices with an active anode area of 9.2 mm2, corresponding to low differential on-resistance of 1.8 $\text{m}\Omega \cdot \text {cm}^{ {2}}$ . The simulation and experimental results show that the proposed device exhibits approximately 2 times JTE dose tolerance window improvement with respect to the breakdown voltage of 4500 V.
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TL;DR: In this article, the authors investigated the failure mechanisms of asymmetric and double trench SiC mosfet transistors under single-pulse unclamped inductive switching (UIS) stress.
Abstract: In this article, commercially 1200-V asymmetric and double trench silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors ( mosfet s) from two manufacturers are investigated by experiment and finite-element simulation under single-pulse unclamped inductive switching (UIS) stress. The variation in avalanche time with mosfet avalanche energy and temperatures dependence of critical avalanche energy and maximum power dissipation are evaluated. It is found that two failure mechanisms are identified, i.e., thermal runaway and gate oxide rupture. For asymmetric trench SiC mosfet s, the failure mode are all thermal runaway at various temperatures. However, the failure mode of double trench SiC mosfet s is thermal runaway or gate oxide rupture, which indicates an instable avalanche robustness under UIS stress. The variations of dc parameters are recorded to evaluate external features of device failure. Furthermore, finite-element simulation is used to reveal the electro-thermal stress inside the device during avalanche. Finally, failed devices are decapsulated to verify the location of failure point from the perspective of the semiconductor die.
35 citations
TL;DR: In this article, a short-circuit capability prediction and failure mode of 1200-V-class SiC MOSFETs with a double and asymmetric trench structure are proposed under single-pulse shortcircuit stress.
Abstract: In this article, short-circuit capability prediction and failure mode of 1200-V-class SiC MOSFET s with a double and asymmetric trench structure are proposed under single-pulse short-circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various dc bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in a short-circuit test. For asymmetric trench SiC MOSFET s, failure modes are gate damage at lower dc bus voltages and thermal runaway at higher dc bus voltages; whereas failure mode for double trench SiC MOSFET s is thermal runaway at all dc bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the dc bus voltage and peak short-circuit current of the device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFET s by the postdecapsulation.
19 citations
TL;DR: In this paper, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2D numerical simulations.
Abstract: In this article, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2-D numerical simulations. The novel N+ island buffer 4H-SiC TG MOSFET and the conventional TG 4H-SiC MOSFET are analyzed and compared to examine whether an N+ island region introduced in the second buffer can effectively reduce the impact ionization located at the N− drift/N+ buffer junction and improve device tolerance to the SEB. The TCAD simulation results revealed that compared with the conventional structure, which is a simple double-buffer structure, the N+ island buffer-hardened structure changed the burnout threshold voltage, improving the SEB performance significantly. In addition, the results proved that the impact ionization played an important role in the SEB triggering mechanism, significantly affecting the SEB performance of the 4H-SiC TG MOSFET. The performance of the hardened N+ island buffer with a different dopant concentration of N-buffer 2 and a size of N+ island is discussed. The specific burnout threshold voltage at the optimal parameters of the proposed structure is 47% higher than that of the conventional structure.
19 citations
TL;DR: In this article, the authors validate the recently developed technology computer-aided design (TCAD) material models for 3C-SiC with measurements on power diodes and create trade-off maps.
Abstract: Major recent developments in growth expertise related to the cubic polytype of Silicon Carbide, the 3C-SiC, coupled with its remarkable physical properties and the low fabrication cost, suggest that within the next years, 3C-SiC devices can become a commercial reality. Inevitably, a comparison to the most well-developed polytype of SiC, the 4H-SiC, should exist. It is, therefore, important to develop finite element method techniques and models for accurate device design, analysis, and comparison. It is also needed to perform an exhaustive investigation with scope to identify which family of devices, which voltage class, and for which applications this polytype is best suited. In this paper, we validate the recently developed technology computer-aided design (TCAD) material models for 3C-SiC and those of 4H-SiC with measurements on power diodes. An excellent agreement between measurements and TCAD simulations was obtained. Thereafter, based on this validation, 3C- and 4H-SiC vertical power diodes are assessed to create trade-off maps. Depending on the operation requirements imposed by the application, the developed tradeoff maps set the boundary of the realm for those two polytypes and allows to predict which applications would benefit once electrically graded 3C-SiC becomes available.
17 citations
TL;DR: In this paper, a U-shaped field-plate (DTUFP) edge-termination structure for 1200-V-class silicon carbide (SiC) devices is presented.
Abstract: In this article, design and characterization of the deep-trench, U-shaped field-plate (DTUFP) edge-termination structure for 1200-V-class silicon carbide (SiC) devices are presented. A systematic numerical analysis shows that the trench depth, trench width, field-plate depth, and field-plate length are the four key structural parameters to determine the voltage blocking capability of the edge-termination structure. Experimental results demonstrate that the breakdown voltage of the proposed edge-termination structure can reach 1380 V when the edge-termination structure is well designed. Liquid crystal thermal measurement and destructive breakdown testing show that the ideal planar junction breakdown voltage has been achieved. The well-designed edge-termination structure has an ultrashort-edge width of 33 $\mu \text{m}$ , which is approximately 75% shorter than that of the conventional guard-ring and junction termination extension (JTE) edge-termination structures.
12 citations
Cites background from "A Multiple-Ring-Modulated JTE Techn..."
...combine MFZ-JTE and RA-JTE were proposed to reduce the dopant sensitivity [6]–[11]....
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References
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05 Sep 2008
TL;DR: In this article, the fundamental physics of power semiconductor devices are discussed and an analytical model for explaining the operation of all power Semiconductor devices is presented, focusing on silicon devices.
Abstract: Fundamentals of Power Semiconductor Devices provides an in-depth treatment of the physics of operation of power semiconductor devices that are commonly used by the power electronics industry. Analytical models for explaining the operation of all power semiconductor devices are shown. The treatment focuses on silicon devicesandincludes the unique attributes and design requirements for emerging silicon carbide devices.
1,730 citations
"A Multiple-Ring-Modulated JTE Techn..." refers background in this paper
...It is found that the breakdown voltage is 4940 V for MRM-JTE device, which is close to 92% of the ideal parallel-plane breakdown voltage [20], [21]....
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TL;DR: In this article, a review of recent progresses in the development of SiC- and GaN-based power semiconductor devices together with an overall view of the state of the art of this new device generation is presented.
Abstract: Wide bandgap semiconductors show superior material properties enabling potential power device operation at higher temperatures, voltages, and switching speeds than current Si technology. As a result, a new generation of power devices is being developed for power converter applications in which traditional Si power devices show limited operation. The use of these new power semiconductor devices will allow both an important improvement in the performance of existing power converters and the development of new power converters, accounting for an increase in the efficiency of the electric energy transformations and a more rational use of the electric energy. At present, SiC and GaN are the more promising semiconductor materials for these new power devices as a consequence of their outstanding properties, commercial availability of starting material, and maturity of their technological processes. This paper presents a review of recent progresses in the development of SiC- and GaN-based power semiconductor devices together with an overall view of the state of the art of this new device generation.
1,648 citations
"A Multiple-Ring-Modulated JTE Techn..." refers background in this paper
...This is mainly due to the high blocking voltage, low specific on-resistance, and high operation junction temperature compared to their silicon counterpart at the same power level [3], [4]....
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Book•
23 Sep 2014
TL;DR: A comprehensive introduction and up-to-date reference to SiC power semiconductor devices covering topics from material properties to applications is provided in this paper. But the authors focus on the SiC Schottky barrier diodes (SBDs) and do not provide an in-depth reference for scientists and engineers working in this field.
Abstract: A comprehensive introduction and up-to-date reference to SiC power semiconductor devices covering topics from material properties to applications Based on a number of breakthroughs in SiC material science and fabrication technology in the 1980s and 1990s, the first SiC Schottky barrier diodes (SBDs) were released as commercial products in 2001. The SiC SBD market has grown significantly since that time, and SBDs are now used in a variety of power systems, particularly switch-mode power supplies and motor controls. SiC power MOSFETs entered commercial production in 2011, providing rugged, high-efficiency switches for high-frequency power systems. In this wide-ranging book, the authors draw on their considerable experience to present both an introduction to SiC materials, devices, and applications and an in-depth reference for scientists and engineers working in this fast-moving field . Fundamentals of Silicon Carbide Technology covers basic properties of SiC materials, processing technology, theory and analysis of practical devices, and an overview of the most important systems applications. Specifically included are:
658 citations
"A Multiple-Ring-Modulated JTE Techn..." refers background in this paper
...most implanted impurities during postimplantation annealing is negligibly small for SiC power devices [14]....
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TL;DR: In this article, a hole to electron ionization coefficient ratio of up to 50 was observed for 4H SiC. This was attributed to the discontinuity of the conduction band for the direction along the c axis.
Abstract: Epitaxial p-n diodes in 4H SiC are fabricated showing a good uniformity of avalanche multiplication and breakdown. Peripheral breakdown is overcome using the positive angle beveling technique. Photomultiplication measurements were performed to determine electron and hole ionization rates. For the electric field parallel to the c-axis impact ionization is strongly dominated by holes. A hole to electron ionization coefficient ratio of up to 50 is observed. It is attributed to the discontinuity of the conduction band of 4H SiC for the direction along the c axis. Theoretical values of critical fields and breakdown voltages in 4H SiC are calculated using the ionization rates obtained.
394 citations
"A Multiple-Ring-Modulated JTE Techn..." refers background in this paper
...It is found that the breakdown voltage is 4940 V for MRM-JTE device, which is close to 92% of the ideal parallel-plane breakdown voltage [20], [21]....
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TL;DR: In this article, a simple consideration of chemistry indicates that NO, generated from the decomposition of N2O, may be a more efficient oxidant of carbon than O2.
Abstract: 4H-SiC(0001), (0001), and (1120) have been directly oxidized by N2O at 1300°C, and metal–oxide–semiconductor (MOS) interfaces have been characterized. The interface state density has been significantly reduced by N2O oxidation on any face, compared to conventional wet O2 oxidation at 1150°C. Planar n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) fabricated on 4H-SiC(0001), (0001) and (1120) faces have shown effective channel mobilities of 26, 43, and 78 cm2/Vs, respectively. Secondary ion mass spectrometry analyses have revealed a clear pileup of nitrogen atoms near the MOS interface. The thickness of the interfacial transition layer can be decreased by N2O oxidation. The crystal face dependence of the interface structure is discussed. A simple consideration of chemistry indicates that NO, generated from the decomposition of N2O, may be a more efficient oxidant of carbon than O2.
193 citations
"A Multiple-Ring-Modulated JTE Techn..." refers background in this paper
...The surface trap is inevitable in the real devices, which originated from electron trapping at shallow acceptorlike interface states in n-SiC (epilayer)/SiO2 or positive charge caused by holes trapped at the energetically deep interface states and the fixed oxide charge in p-SiC (JTE region)/SiO2 interface [18], [19]....
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