A network-on-chip-based turbo/LDPC decoder architecture
12 Mar 2012-pp 1525-1530
TL;DR: This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design of multi-standard decoders.
Abstract: The current convergence process in wireless technologies demands for strong efforts in the conceiving of highly flexible and interoperable equipments. This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design of multi-standard decoders. High level modeling is exploited to drive the NoC optimization for a given set of both turbo and Low-Density-Parity-Check (LDPC) codes to be supported. Moreover, synthesis results prove that the proposed approach can offer a fully compliant WiMAX decoder, supporting the whole set of turbo and LDPC codes with higher throughput and an occupied area comparable or lower than previously reported flexible implementations. In particular, the mentioned design case achieves a worst-case throughput higher than 70 Mb/s at the area cost of 3.17 mm2 on a 90 nm CMOS technology.
Citations
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TL;DR: This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding, tackling the reconfiguration issue and introducing a formal and systematic treatment that was not previously addressed.
Abstract: Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed and ii) proposing a reconfigurable NoC-based turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case.
57 citations
Cites background or methods from "A network-on-chip-based turbo/LDPC ..."
...The LDPC decoding core used in the decoder described in [14] relies on a serial architecture suited for exclusive memory usage....
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...This work stems from the results presented in [14], improving the architectures through novel memory scheduling and addressing methods, reduced latency and simpler control....
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...In [9]–[11], flexibility is achieved through the design of processing elements (PEs) based on application-specific-instruction-set-processor (ASIP) architectures, whereas in [12]–[14] PEs rely on application-specific-integrated-circuit (ASIC) solutions....
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...Memory organization evolves from the idea presented in [14], in which in every decoding core two memories are instantiated: a 7-bit memory and a 5-bit memory....
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...Stemming from the work presented in [14], [19], [20], where an ASIC implementation of an NoC-based turbo/LDPC decoder architecture is proposed, this paper aims to further investigate and optimize it....
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TL;DR: This article presents the first dedicated approach that finds conflict free memory mapping forevery type of codes and for every type of parallelism in polynomial time and could enable memory mapping algorithm to be embedded on chips and executed on the fly to support multiple block lengths and standards.
Abstract: To meet the higher data rate requirement of current and future communication standards, numerous techniques to decode Turbo and LDPC codes on hardware architecture are developed. Unfortunately, interleaving laws that are used in these codes often result in memory access conflicts when massively parallel architectures are targeted which considerably limits the throughput. In this article, the first dedicated approach that finds conflict free memory mapping for every type of codes and for every type of parallelism in polynomial time is presented. The implementation of this highly efficient algorithm shows significant improvement in terms of computational time compared to state of the art approaches. Ultimately, this could enable memory mapping algorithm to be embedded on chips and executed on the fly to support multiple block lengths and standards.
21 citations
Cites background from "A network-on-chip-based turbo/LDPC ..."
...In [42], [43], extensive study has been performed to determine the performance of different network on Chip (NoC) topologies in the context of decoder architectures whereas [44] presents an architecture to generate addresses for HSPA interleaver using different conflict management mechanisms....
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01 Jun 2014
TL;DR: In this chapter, an overview of architecture of turbo and LDPC codes is presented, the standard implementation of those codes is first presented, and architecture for high-speed, low-power, and high flexibility are derived.
Abstract: The transition from analog telecommunication equipment and terminals to digital systems and, more recently, the fast development of wireless communications were made possible by three factors: 1) key advances in integrated circuit technology, 2) large improvements in methodologies and tools for the design of highly complex digital circuits, and 3) progress in information theory, in particular, the belief propagation algorithm that allows error control codes operating close to the Shannon limit. In this chapter, an overview of architecture of turbo and LDPC codes is presented. The standard implementation (i.e., low complexity) of those codes is first presented. Then architecture for high-speed, low-power, and high flexibility are derived. Finally, the chapter concludes with the presentation of exotic decoding architectures and a survey of relevant architectures.
Keywords
13 citations
Cites background or methods from "A network-on-chip-based turbo/LDPC ..."
...Finally, the design of a complete fully flexible NOC based decoder for both turbo and LDPC codes is described in [50] [5]....
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...This idea was later developed and deeply investigated to efficiently support virtually any turbo and LDPC codes [49] [5] [50], with almost no penalty in terms of throughput, with respect to implementations optimized for a specific class of codes....
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...The RIBB decoder can be viewed as a very simple Network-on-Chip (NoC) based decoder, where the 43 ring topology offers lower implementation complexity than other networks, such as for example the crossbar–switch....
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...Examples of fully flexible solutions are the efficient nonblocking Benes networks [4] and application specific NoCs (Network on Chip) [5]....
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TL;DR: An overview of state-of-the-art in the design of flexible LDPC decoders is provided and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.
Abstract: Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.
11 citations
TL;DR: Fourth-generation communications systems call for a high amount of computational power due to multiantenna and multimode features, and several alternatives have been partially explored to implement flexible base-band building blocks and a lot of research is still required to bring efficiency into programmable platforms.
Abstract: Fourth-generation communications systems call for a high amount of computational power due to multiantenna and multimode features. The level of flexibility required is growing rapidly with the number of modes to be supported for a single protocol and the number of protocols to be supported by a single receiver. Such high level of flexibility becomes a key feature of new and legacy radio applications in many domains (military radio, broadcast systems, aeronautic communications, etc.), which call for adopting a software-defined radio (SDR) approach, or even for incorporating additional adaptive capabilities, such as suggested by cognitive radio (CR) research. In general, the design of flexible base-band platforms raises several critical problems, including the high level of required performance, the dissipated power, and the reconfiguration process itself. Several alternatives have been partially explored to implement flexible base-band building blocks and a lot of research is still required to bring efficiency into programmable platforms.
8 citations
References
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Book•
01 Jan 1963TL;DR: A simple but nonoptimum decoding scheme operating directly from the channel a posteriori probabilities is described and the probability of error using this decoder on a binary symmetric channel is shown to decrease at least exponentially with a root of the block length.
Abstract: A low-density parity-check code is a code specified by a parity-check matrix with the following properties: each column contains a small fixed number j \geq 3 of l's and each row contains a small fixed number k > j of l's. The typical minimum distance of these codes increases linearly with block length for a fixed rate and fixed j . When used with maximum likelihood decoding on a sufficiently quiet binary-input symmetric channel, the typical probability of decoding error decreases exponentially with block length for a fixed rate and fixed j . A simple but nonoptimum decoding scheme operating directly from the channel a posteriori probabilities is described. Both the equipment complexity and the data-handling capacity in bits per second of this decoder increase approximately linearly with block length. For j > 3 and a sufficiently low rate, the probability of error using this decoder on a binary symmetric channel is shown to decrease at least exponentially with a root of the block length. Some experimental results show that the actual probability of decoding error is much smaller than this theoretical bound.
11,592 citations
"A network-on-chip-based turbo/LDPC ..." refers methods in this paper
...Wireless communications employ high-performance forward error correction codes as turbo [1] and Low-DensityParity-Check (LDPC) [2] codes to achieve reliable transmission....
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Proceedings Article•
01 Jan 1993
7,742 citations
23 May 1993
TL;DR: In this article, a new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed.
Abstract: A new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed. The turbo-code encoder is built using a parallel concatenation of two recursive systematic convolutional codes, and the associated decoder, using a feedback decoding rule, is implemented as P pipelined identical elementary decoders. >
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01 Jan 2000
TL;DR: This paper presents an architectural study of a scalable system-level interconnection template, and discusses the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services.
Abstract: This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not meet the performance requirements of tomorrow's systems. We present an alternative interconnection in the form of switching networks. This technology originates in parallel computing, but is also well suited for heterogeneous communication between embedded processors and addresses many of the deep submicron integration issues. We discuss the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services. Eventually we present our first results on the cost/performance assessment of an integrated switching network.
995 citations
"A network-on-chip-based turbo/LDPC ..." refers methods in this paper
...Stemming from the general Network-on-Chip (NoC) paradigm [10], Neeb et alii [11] proposed an interesting NoCbased approach to enable flexible and efficient interconnection among the processing elements in parallel turbo decoder architectures....
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TL;DR: The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from performance, latency, computational-complexity, and memory-requirement perspectives.
Abstract: Various log-likelihood-ratio-based belief-propagation (LLR-BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representations of the decoding computations are shown to achieve a reduction in complexity by simplifying the check-node update, or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from performance, latency, computational-complexity, and memory-requirement perspectives.
989 citations
"A network-on-chip-based turbo/LDPC ..." refers background or methods in this paper
...According to [21], the Ψ(·) function in (7) and (9) can be simplified with a limited BER performance loss as...
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...Then, Qlk[c] values are compared sequentially in the Minimum Extraction Unit (MEU) to find the first two minimum values (11) [21]....
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