A new algorithm with minimum track for four layer channel routing in VLSI design
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...REFERENCES [1] Ajoy Kumar Khan and Bhaskar Das, "A New Algorithm with Minimum Track for Four Layer Channel Routing in VLSI Design" in proc. of IEEE International Conference on Computer Communication and Informatics, Coimbatore, pp. 1-5, 2013....
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..."Via Minimization For Multilayer Channel Routing in VLSI Design" Bhaskar Das, Ashim Kumar and Ajoy Kumar Khan[31] 2014 IEEE Fourth International Conference on Communication Systems and Network Technologies....
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...[31] Bhaskar Das, Ashim Kumar Mahato and Ajoy Kumar Khan, "Via Minimization For Multi-layer Channel Routing In VLSI Design" in proc. of IEEE Communication Systems and Network Technologies (CSNT), pp. 1036-1039, April 2014....
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...algorithms with Minimum Tracks for Four Layer Channel Routing in VLSI Design"Ajoy Kumar Khan , Bhaskar Das [1] 2013 IEEE...
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...N O O F TR A C K S C H A N N EL LE N G TH A C H IE V EM EN TS LI M IT A TI O N S/ TR A D EO FF FU TU R E S C O PE R EM A R K S "A New algorithms with Minimum Tracks for Four Layer Channel Routing in VLSI Design"Ajoy Kumar Khan , Bhaskar Das [1] 2013 IEEE ICCCI C Programming language Vertical Constraint Graph(VCG), Horizontal Constraint Graph(HCG) Horizontal non Constraint Graph(HNCG) 50% of reduction in number of tracks Reduced the no. of tracks needed for channel routing problem then automatically the area of an IC chip is also reduced There is no close loop in the VCG of that channel that means the VCG must be tree If there is a cycle in VCG. a) Add a vertical layer....
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