A new algorithm with minimum track for four layer channel routing in VLSI design
21 Feb 2013-pp 1-5
TL;DR: This work proposes a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers) and converts a two-layer channel routing problem into a four-layerChannel routing problem using HNCG and VCG of the channel.
Abstract: Channel routing is a key problem in VLSI physical design. The main goal of the channel routing problem is to reduce the area of an IC chip. If we concentrate on reducing track number in channel routing problem then automatically the area of an IC chip will be reduced. Here, we propose a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers). To be more specific, through this algorithm we convert a two-layer channel routing problem into a four-layer channel routing problem using HNCG and VCG of the channel. Next, we show the experimental results and graphical structure of that solution.
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01 Jul 2020
TL;DR: SoC KPIs are analyzed and developed script using the TCL scripting language to easily understand SoC KPIS information and the Synopsys ICC2 compiler is used to execute and analyze script.
Abstract: Modern SoC(System-on-Chip)designs key goal is to attain high efficiency and effective resource utilization. But achieving such an objective is a challenging and time-consuming one, development challenge owing to partitioning decisions. Based on decision taken during partition, connectivity between blocks of the SoC must always be configured in such a way that the total performance, for both processing and communication, is fast. Connectivity depends on the SoC Key Performance Indicators (KPIs) like pin assignment, channel estimation between blocks and Feedthrough information. In this paper, SoC KPIs are analyzed and developed script using the TCL scripting language to easily understand SoC KPIs information. The Synopsys ICC2 compiler is used to execute and analyze script. TCL is used by many Synopsys command shells as a scripting tool for automating the design processes. And Graphical User Interface (GUI) provides tools for visualizing design data and analyzing results.
5 citations
01 Jan 2014
TL;DR: This paper analyzes different single-layer algorithms, two- Layer algorithms and three layer algorithms and concludes that the objective of the routing problems like crosstalk, wire length, channel length, no of tracks and vias is to reduce the area of an integrated chip.
Abstract: Routing is one of the most complex stage in physical design. Detailed routing determines the exact place of tracks and via. The main objective ofdetailed routing is to reduce the area of an integrated chip . Minimization of wire length,number of tracks, channel length, congestion factor is the key problem in physical design. Routing is a process to interconnect all the nets within the channel considering all constraints(horizontal and vertical constraints) of that channel. Unlike traditional routing schemes ,all the traffic is along a single path, multipath routing scheme splitthe traffic among several paths in order to reduce the congestion. In this paper, we analyze different single-layer algorithms, two-layer algorithms and three layer algorithms and conclude that the objective of the routing problems like crosstalk, wire length, channel length, no of tracks and vias.
1 citations
Cites methods from "A new algorithm with minimum track ..."
...REFERENCES [1] Ajoy Kumar Khan and Bhaskar Das, "A New Algorithm with Minimum Track for Four Layer Channel Routing in VLSI Design" in proc. of IEEE International Conference on Computer Communication and Informatics, Coimbatore, pp. 1-5, 2013....
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..."Via Minimization For Multilayer Channel Routing in VLSI Design" Bhaskar Das, Ashim Kumar and Ajoy Kumar Khan[31] 2014 IEEE Fourth International Conference on Communication Systems and Network Technologies....
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...[31] Bhaskar Das, Ashim Kumar Mahato and Ajoy Kumar Khan, "Via Minimization For Multi-layer Channel Routing In VLSI Design" in proc. of IEEE Communication Systems and Network Technologies (CSNT), pp. 1036-1039, April 2014....
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...algorithms with Minimum Tracks for Four Layer Channel Routing in VLSI Design"Ajoy Kumar Khan , Bhaskar Das [1] 2013 IEEE...
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...N O O F TR A C K S C H A N N EL LE N G TH A C H IE V EM EN TS LI M IT A TI O N S/ TR A D EO FF FU TU R E S C O PE R EM A R K S "A New algorithms with Minimum Tracks for Four Layer Channel Routing in VLSI Design"Ajoy Kumar Khan , Bhaskar Das [1] 2013 IEEE ICCCI C Programming language Vertical Constraint Graph(VCG), Horizontal Constraint Graph(HCG) Horizontal non Constraint Graph(HNCG) 50% of reduction in number of tracks Reduced the no. of tracks needed for channel routing problem then automatically the area of an IC chip is also reduced There is no close loop in the VCG of that channel that means the VCG must be tree If there is a cycle in VCG. a) Add a vertical layer....
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15 Jan 2020
1 citations
References
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TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.
539 citations
TL;DR: It is shown that an efficient optimal algorithm for interconnecting two rows of points across an intervening channel is unlikely to exist by establishing that this problem is NP-complete.
Abstract: Interconnecting two rows of points across an intervening channel is an important problem in the design of LSI circuits. The most common methodology for producing such interconnections uses two orthogonal layers of parallel conductors and allows wires to "dogleg" arbitrarily. Although effective heuristic procedures are available for routing channels with this methodology, no efficient optimal algorithm has yet been discovered for the general case problem. We show that such an algorithm is unlikely to exist by establishing that this problem is NP-complete.
209 citations
TL;DR: YACR2 is a channel router that minimizes the number of through vias in addition to the area used to complete the routing in a two-layer channel.
Abstract: YACR2 is a channel router that minimizes the number of through vias in addition to the area used to complete the routing in a two-layer channel. It can route channels with cyclic constraints and uses a virtual grid. YACR2 uses preferably one layer for the horizontal segments of the nets and the other for the vertical ones but it may require the routing of a few horizontal segments in the second layer. Experimentally YACR2 performs better than any of the channel routers proposed thus far both in terms of area used and through vias. It routed the Deutsch Difficult Example in density with substantially less vias than Burstein's hierarchical router and with the default parameter values in less than 3 s of CPU time on a VAX 11/780.
161 citations
TL;DR: Two special types of three-layer channel routing, VHV and HVH, are introduced in this paper, and the merging algorithm and the left edge algorithm used in two-layer routing can be extended to three layers.
Abstract: With the advent of VLSI technology, multiple-layer routing becomes feasible. Two special types of three-layer channel routing, VHV and HVH, are introduced in this paper. The merging algorithm and the left edge algorithm used in two-layer routing can be extended to three layers. Attempts are made to compare the lower bounds of channel width of three types of routing--two-layer, VHV, and HVH. The algorithms were coded in PASCAL and implemented on VAX 11/780 computer. The computational results are satisfactory, since all the results lead to a further reduction in routing area.
105 citations
02 Jul 1986
TL;DR: A three-dimensional maze router is used which guarantees that any problem can be routed even when cyclic constraints are present, and produces optimal results on a wide range of industrial and academic examples for any number of layers and pitch combinations.
Abstract: New techniques for routing general multi-layer channels are introduced. These techniques can handle a variety of technology constraints. For example, linewidth and line-to-line spacing can be specified independently for each layer, and contact stacking can be allowed or forbidden. These techniques have been implemented in a new multi-layer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problem into two and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2. In particular a three-dimensional maze router is used which guarantees that any problem can be routed even when cyclic constraints are present. Chameleon produces optimal results on a wide range of industrial and academic examples for any number of layers and pitch combinations.
45 citations