A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism
TL;DR: In this paper, a double gate tunnel field effect transistor (TFET) was used for the formation of novel double gate TFET, where the initially heavily doped n + substrate is converted into n + - i - n + + - n+ - i (Drain-Channel-Source) by the selection of appropriate work functions of control gate (CG) and polarity gate (PG) as 4.7 eV.
About: This article is published in Superlattices and Microstructures.The article was published on 2016-10-01. It has received 24 citations till now. The article focuses on the topics: Tunnel field-effect transistor & Subthreshold slope.
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TL;DR: In this paper, a junctionless tunnel field effect transistor with a dual material gate and a heterostructure channel/source interface (DMG-H-JLTFET) is investigated.
49 citations
TL;DR: In this article, a dual-material control gate with dual-oxide tunnel field effect transistor is investigated to overcome the problem of fabrication complexity and to reduce the cost of microelectronic devices.
Abstract: To overcome the problem of fabrication complexity and to reducei the cost of microelectronic devices, a new concept of dual-material control gate with dual-oxide tunnel field-effect transistor is investigated. A stack gate approach is applied to reduce the width of tunneling barrier at source–channel junction. Use of dual oxides at source–channel interface provides improved capacitive coupling, which enhances the on-state current. The entire gate segment has been partitioned into three parts, namely tunnel gate $$(M_1)$$, control gate $$(M_2)$$ and auxiliary gate $$(M_3)$$ with different work functions such as $$\phi _{1}$$, $$\phi _{2}$$ and $$\phi _{3}$$. In this context, to keep dual-work functionality, the feasible combinations of these work functions are adopted. Technology computer- aided design (TCAD) simulations of these proposed combinations of work functions along with dual oxides provide better results for the combinations of $$(\phi _1=\phi _3<\phi _2)$$. In addition, comparison between these combinations on the basis of analog/RF performance is done in this work. This work shows improved analog/RF parameters such as $$g_\text {m}, C_\text {gs}, C_\text {gd}, f_\text {T}$$ and TFP, and linearity parameters including $$g_\text {m3}, \text {VIP3, IIP3}$$ and $$\text {IMD3}$$ for the proposed device DMDODG-TFET (dual-material dual-oxide double-gate TFET). The use of this proposed device structure reduces the ambipolar behavior and subthreshold swing $$(18.5\,\text {mV}/\text {deacde})$$, and enhances the on-current [$$3.6\times 10^{-5}\,(A/\upmu \text {m})$$] significantly, making it suitable for analog/RF and linearity applications.
44 citations
TL;DR: In this paper, a carbon nanotube junctionless tunnel field effect transistor (CNT-TFET) has been proposed and investigated, which uses two isolated gates with the same work function (main gate (MG) and P-gate (PG)) which are separated by a 3'nm SiO2 spacer.
29 citations
TL;DR: In this article, the authors explored the performance of different SE metal silicide such as TiSi2, CrSi2 and Pd2Si in junctionless TFETs and revealed that the depletion of hole plasma (formation of Schottky interface) appears near the SE/p+ induced source interface.
Abstract: Tunnel Field Effect Transistors (TFET) based on quantum mechanical band to band tunneling (BTBT) are promising alternatives for low power analog applications. Additionally, the concept of junctionless (JL) devices realized by the charge plasma concept offers added advantages in terms of simplified fabrication techniques. In n type JL-TFET, p+ source is induced using a polarity gate (PG) with suitable work function. However, retention of induced p+ source is not a sole contribution of PG, the source electrode (SE) metal silicide work function also plays a significant role in the retention of hole plasma (specially near the interface of SE/induced source). Thorough study regarding the combined influence of PG and SE metal silicide work function on induced p+ source is missing in the literatures. This work explores the performance of JL-TFET of different SE metal silicide such as TiSi2 (4.53 eV), CrSi2 (4.85 eV) and Pd2Si (5.3 eV). It is perceived that for SE metal silicide with work function lower than p+ induced source i.e., TiSi2 and CrSi2 the depletion of hole plasma (formation of Schottky interface) appears near the SE/p+ induced source interface. The depletion of hole plasma is attributed to the combined electric field of SE metal silicide and the PG, the immediate consequence is the refrainment of current. Further, due to the formation of Schottky interface for TiSi2 and CrSi2, the performance of the device is examined by revoking and evoking the Universal Schottky Tunneling (UST) model. Results reveal the undervalued performance of the device without the inclusion of UST, primarily a lower drain current (and thereby the analog performance) of the device is obtained, since it ignores the Schottky tunneling at SE/p+ induced source interface. However, the inclusion of UST model emulates the performance of JL-TFET precisely, by incorporating the Schottky tunneling at the SE/p+ induced source interface. Thus, for the retention of hole plasma, appropriate SE work function i.e., ΦSE > Φp+ induced source is required, whereas for SE work function ΦSE < Φp+ induced source appropriate Schottky tunneling must be considered for accurate analysis of the device. The study also reveals that the depletion of hole plasma and hence the formation of Schottky interface can be avoided using SE with metal work function source for which consideration of UST is immaterial.
23 citations
TL;DR: In this article, a P+ (source)-I (channel)-N (drain) type structure has been considered, wherein a metal electrode is deposited over the source region, and a negative voltage is applied to the source electrode (SE).
18 citations
References
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25 Oct 2010
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.
1,389 citations
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
Book•
17 Oct 2007
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.
Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.
843 citations
01 Dec 2008
TL;DR: In this paper, a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS < 60 mV/dec was experimentally demonstrated.
Abstract: The main challenges for Tunnel FETs are experimentally demonstrating SS<60 mV/dec, high ON currents and solving their ambipolar behavior. We have experimentally demonstrated a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS<60 mV/dec. Due to small bandgap of s-Ge and the electrostatics of the DG structure, record high drive current of 300 uA/um (the highest ever reported experimentally for a TFET) and a subthreshold slope of ~50 mV/dec was observed. In addition, to address the ambipolar problem and examine the scalability of TFETs, we have developed a sophisticated TFET simulator that uses a Quantum transport model, Non-local BTBT, complete Bandstructure (real and complex) information, and includes all transitions (direct and phonon assisted). Using this simulator, we have studied the scalability of three asymmetric DG TFET configurations (underlapped drain, lower drain doping and lateral heterostructure) in terms of their ability to solve the ambipolar behavior and achieve high ON and low OFF currents.
515 citations
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.
428 citations