Journal ArticleDOI
A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation
Te-Liang Lee,Yi-Hung Tsai,Wun-Jie Lin,Hsiao-Lan Yang,Chiu-Wang Lien,Chrong Jung Lin,Ya-Chin King +6 more
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TLDR
A novel differential p-channel logic-compatible multiple-time programmable (MTP) memory cell that performs differential read to increase the on/off window, and a novel self-recovery operation is implemented to boost the floating gate level, thus avoiding the charge-loss problem due to the thin gate oxide requirement in advance logic nonvolatile memory applications.Abstract:
This letter presents a novel differential p-channel logic-compatible multiple-time programmable (MTP) memory cell. This MTP cell has a pair of floating gates, and performs differential read to increase the on/off window. Additionally, a novel self-recovery operation is implemented to boost the floating gate level, thus avoiding the charge-loss problem due to the thin gate oxide requirement in advance logic nonvolatile memory applications. This differential cell with its self-recovery operation is a very promising MTP solution for gate oxide layer with a 70 A thickness, and can be implemented by 3.3 V I/O in 90 nm and the advanced CMOS logic processes such as 45 nm and beyond.read more
Citations
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Journal ArticleDOI
Half-MOS Single-Poly EEPROM Cell in Standard CMOS Process
TL;DR: In this article, a novel multiple-time programmable (MTP) single-poly EEPROM cell based on a half-MOS device is presented, which is fabricated in a standard complementary metal-oxide-semiconductor (CMOS) process without any additional mask or process step.
Journal ArticleDOI
A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process
Chiu-Wang Lien,Haw-Yun Wu,Cheng-Wei Tsai,Chen-Mei Huang,Yue-Der Chih,Te-Liang Lee,Chrong Jung Lin +6 more
TL;DR: A new fully logic process compatible 2T multitime programmable (MTP) memory cell has been introduced for embedded logic nonvolatile memory (NVM) applications and adopts a novel contact coupling gate structure as an additional control gate for highly efficient operation and high-density memory applications.
Journal ArticleDOI
Multitime Programmable Memory Cell With Improved MOS Capacitor in Standard CMOS Process
TL;DR: In this article, a multitime programmable memory cell with an improved MOS capacitor has been proposed, which has p-type junction near the channel, which prevents the capacitor from deep depletion and improves the cell's program/erase efficiency and stability.
Journal ArticleDOI
A High-Density MTP Cell With Contact Coupling Gates by Pure CMOS Logic Process
TL;DR: Very small cell size, fast programming speed, and superior reliability characteristic make the new contact coupling gate MTP cell be one of the most promising solutions in advanced logic NVM application.
Journal ArticleDOI
Half-MOS Based Single-Poly EEPROM Cell With Program and Erase Bit Granularity
TL;DR: A single-poly electrically erasable programmable ROM (EEPROM) cell compatible with standard CMOS process and based on a novel writing-inhibition scheme enabled by the combination of the body effect with multiple half-MOS devices is proposed.
References
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Proceedings ArticleDOI
A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology
TL;DR: In this article, a novel embedded one-time programmable (OTP) nonvolatile memory (NVM) using only standard Foundry CMOS logic technology is described, and reliability data is presented for 1Mb memory modules fabricated in 0.18mu technology.
Journal ArticleDOI
A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller
TL;DR: This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications.
Journal ArticleDOI
A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide
TL;DR: In this paper, a memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed, which achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time.
Patent
Pfet nonvolatile memory
TL;DR: In this paper, a nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine the state of the cell.
Patent
Electrically erasable programmable logic device
TL;DR: An electrically erasable programmable logic device as discussed by the authors includes a P-type substrate, a first N-type doped region located inside the P type substrate, and a first gate located on the P- type substrate.