A new look at yield of integrated circuits
01 Aug 1970-Vol. 58, Iss: 8, pp 1290-1291
TL;DR: In this paper, the authors derived expressions for integrated-circuit yield as a function of active circuit area, using as a model random distributions of indistinguishable spot defects, and used a nonrandom distribution of distinguishable spot defects as their model.
Abstract: Expressions are derived for integrated-circuit yield as a function of active circuit area, using as a model random distributions of indistinguishable spot defects. Previous attempts to calculate integrated-circuit yield have used a nonrandom distribution of distinguishable spot defects as their model.
Citations
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IBM1
TL;DR: In this paper, the random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process, which allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing.
Abstract: The random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process. This approach allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing. Some simpler formulations of yield theory that have been described in the literature are compared to the model. Application of the model to yield management are discussed and examples given.
432Â citations
TL;DR: In this article, the development and refinement of net-die-per-wafer yield models during the past 25 years are reviewed, and the models are tested for accuracy by comparison with actual yield data from seven separate chip companies.
Abstract: The development and refinement of net-die-per-wafer yield models during the past 25 years are reviewed, and the models are tested for accuracy by comparison with actual yield data from seven separate chip companies. Depending on chip size, the more accurate models are the Poisson and the negative binomial. Several models for line yields in wafer fabrication are also covered. For predicting yields of larger-die-area very large-scale integration, the negative binomial model is the more accurate, but its use many require experimental determination of alpha, sometimes called the cluster parameter, versus chip area for the particular process and factory environment of interest. How an Insystems holographic wafer inspection machine can aid this process is described. Financial payback calculations for cleaner processing machines and experience curve effects on yields are also discussed. >
309Â citations
IBM1
TL;DR: This paper shows how the yield for any product can be calculated given the critical areas, defect density, and mixing parameter.
Abstract: A model with mixed Poisson statistics has been developed for calculating the yield for memory chips with redundant lines and for partially good product. The mixing process requires two parameters which are readily obtained from product data. The product is described in the model by critical areas which depend on the circuit's sensitivity to defects, and they can be determined in a systematic way. The process is represented in the model by defect densities and gross yield losses. These are measured with defect monitors independently of product type. This paper shows how the yield for any product can be calculated given the critical areas, defect density, and mixing parameter. Future yields are forecast by using expected improvements in defect densities. Examples show good agreement between actual and calculated yields.
241Â citations
01 Sep 1998
TL;DR: A detailed survey of yield-enhancement techniques for very large-scale-integration (VLSI) circuits can be found in this article, where the authors provide a detailed survey and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.
Abstract: Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.
236Â citations
01 Aug 1999
TL;DR: In this article, the authors present an overview of yield, reliability, burn-in, cost factors, and fault coverage as practiced in the semiconductor manufacturing industry, and their advantages and disadvantages are discussed.
Abstract: This paper presents an overview of yield, reliability, burn-in, cost factors, and fault coverage as practiced in the semiconductor manufacturing industry. Reliability and yield modeling can be used as a foundation for developing effective stress burn-in, which in turn can warranty high-quality semiconductor products. Yield models are described and their advantages and disadvantages are discussed. Both yield reliability relationships and relation models between yield and reliability are thoroughly analyzed in regard to their importance to semiconductor products.
127Â citations
Cites background from "A new look at yield of integrated c..."
...Price [ 75 ] derived the same result by considering the total number of ways indistinguishable defects can be distributed among chips....
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References
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01 Dec 1964
TL;DR: In this article, a generalized cost-size relationship is derived for a monolithic circuit consisting of N identical components, taking into account variations in component density, yield, and assembly costs with N. The results indicate that when systems requirements make it desirable to include larger numbers of components in one package than the optimum for one monolith, wired-chip schemes are preferable to single monoliths, the optimum chip size being smaller than that for a simple monolith.
Abstract: A generalized cost-size relationship is derived for a monolithic circuit consisting of N identical components, taking into account variations in component density, yield, and assembly costs with N. It is intended to reveal cost trends rather than give accurate results for specific cases and deals only with fabrication costs. A yield-area relationship is used which takes into account chip-to-chip variations in defect density. It is found that the ratio (circuit cost per component/cost of discrete transistor) is a minimum at a chip size which is determined primarily by the spot defect density on the device. This optimum chip size lies between approximately 20 and approximately 60 mils square for a wide range of parameter values. State-of-the-art parameter values indicate a potential order of magnitude cost saving in integrated circuits compared with discrete transistors. The minimum value for the cost ratio is in general inversely proportional to the maximum packing density of components on a semiconductor slice and has a limiting value approximately 1/8N, N 0 being the number of components which can be packed on the chip size normally used for transistors. Arrays of identical logic gates fit the circuit model used quite closely, and the curves indicate that the cost per gate in reasonably densely packed arrays can be less than the cost of a discrete transistor. The results also indicate that when systems requirements make it desirable to include larger numbers of components in one package than the optimum for one monolith, wired-chip schemes are preferable to single monoliths, the optimum chip size being smaller than that for a simple monolith.
375Â citations
Proceedings Article•
01 Jan 196789Â citations
TL;DR: In this paper, the average yield for N multiple devices as a function of the average yields of single devices was calculated assuming several simple forms of distribution function for slice yields, and it was shown that the usual calculation is too pessmistic by an appreciable factor even when no within slice correlation exists.
Abstract: This correspondence calculates the average yield \bar{Y_{N}} for N multiple devices as a function of the average yield ( \bar{Y_{1}} ) of single devices assuming several simple forms of distribution function for slice yields. It shows that the usual calculation \bar{Y_{N}} = ( \bar{Y_{1}})^{N} is too pessmistic by an appreciable factor even when no "within slice" correlation exists. Using an actual distribution of transistor slice yields, the ( \bar{Y_{1}})^{N} calculation is shown to give a yield which is a factor of 5 too low for groups of eight good devices.
35Â citations