A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs
TL;DR: In this paper, the authors describe a system based on partial reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs, which uses the internal configuration capabilities that modern FPGA offer in order to inject SEU within configuration memory.
Abstract: Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing complex system. Unfortunately, SRAM-based FPGAs are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to successfully deploy safety- or mission-critical applications, designer need to validate the correctness of the obtained designs. In this paper we describe a system based on partial-reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs. The proposed fault-injection system uses the internal configuration capabilities that modern FPGAs offer in order to inject SEU within the configuration memory. Detailed experimental results show that the technique is orders of magnitude faster than previously proposed ones.
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TL;DR: In this paper, a methodology to perform automatic selective TMR insertion on digital circuits is presented, having as a constraint the required reliability level, which is guaranteed while reducing the area compared to TMR.
Abstract: In this paper, a methodology to perform automatic selective TMR insertion on digital circuits is presented, having as a constraint the required reliability level. Such reliability is guaranteed while reducing the area compared to TMR. In addition, a performance enhancement is proposed in order to guarantee a computation time feasible for this automatic selective TMR insertion methodology. It focuses on the choice of a starting point close enough to an optimal solution. The method consists in the analysis of the topological features of the target circuit which will help the optimization engine to identify those flip-flops more susceptible to be tripled depending on the showed sensitivity to SEUs.
65 citations
Cites background from "A New Partial Reconfiguration-Based..."
...The main idea is to recover the original programmed information after an upset [6]....
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03 Oct 2012
TL;DR: A novel platform is proposed which requires a single FPGA to perform the fault injection, to apply input vectors and to evaluate the correctness of the outputs, and works at a very high speed, being able to inject and remove a fault in under 10μs.
Abstract: Evaluating the resilience of a given circuit against adverse effects, such as radiation-induced single event upsets, is a complex and frequently time-demanding task. For Field Programmable Gate Arrays (FPGAs), this task has the additional complexity of accounting for faults affecting the configuration memory. For this reason, several works propose techniques to inject and evaluate faults affecting configuration bits. In this work, we propose a novel platform which requires a single FPGA to perform the fault injection, to apply input vectors and to evaluate the correctness of the outputs. It can evaluate complex fault models, such as multiple bit errors that are caused by a single bit flip. Furthermore, it occupies a small portion of the device resources and works at a very high speed, being able to inject and remove a fault in under 10μ8.
54 citations
31 Aug 2011
TL;DR: The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Virtex5 for different types of RTL circuits and fault tolerant architectures.
Abstract: In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bit stream through the JTAG interface and subsequent dynamic reconfiguration of FPGA. It allows to select region of the FPGA for SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Virtex5 for different types of RTL circuits and fault tolerant architectures. The experimental results demonstrated the effectiveness of the methodology.
51 citations
Cites methods from "A New Partial Reconfiguration-Based..."
...It is important to say that some tools based on the use of ICAP to insert SEUs into FPGA bitstream exist [18],[19]....
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TL;DR: This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique that utilizes debugging facilities of Altera FPGAs in order to inject single event upset and multiple bit upset fault models in both flip-flops and memory units.
49 citations
Cites background or methods from "A New Partial Reconfiguration-Based..."
...This paper proposes an instrumentation-based fault injection technique which completely relies on commercial tools for the placement of saboteurs....
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...Feature size shrinkage in nowadays integrated circuits results in reduction of capacitance per transistor, and as a consequence particles with lower energy, which are far more plentiful, can generate sufficient charge to cause soft errors [1,2]....
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...…Technology, Tehran, Iran b Karlsruhe Institute of Technology, Karlsruhe, Germany a r t i c l e i n f o a b s t r a c t Article history: Received 17 July 2013 Received in revised form 4 November 2013 Accepted 2 January 2014 Available online 31 January 2014 By technology down scaling in nowadays…...
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...All rights reserved....
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TL;DR: In this paper, an approach combining the SRAM-based field-programmable gate array static cross-section with the results of fault injection campaigns allows predicting the error rate of any implemented application.
Abstract: An approach combining the SRAM-based field-programmable gate array static cross-section with the results of fault injection campaigns allows predicting the error rate of any implemented application. Experimental results issued from heavy ion tests are compared with predictions to validate the proposed methodology.
44 citations
References
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10 Sep 2001
TL;DR: In this paper, the authors present the meaningful results of a single bit upset fault injection analysis performed in Virtex FPGA triple modular redundancy (TMR) design, each programmable bit upset able to cause an error in the TMR design has been investigated.
Abstract: This paper presents the meaningful results of a single bit upset fault injection analysis performed in Virtex FPGA triple modular redundancy (TMR) design. Each programmable bit upset able to cause an error in the TMR design has been investigated. Final conclusion using the TMR "golden" comparison method shows that "no errors" were reported by Virtex TMR design implementation in the presence of single bit upsets in the customization logic. The proton radiation ground test has confirmed the results achieved by fault injection.
130 citations
"A New Partial Reconfiguration-Based..." refers background in this paper
...As an alternative to expensive radiation testing, several fault-injection approaches were recently proposed [5]–[7]....
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TL;DR: Radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions shows the FPGA look-up table (LUT) resources are the most sensitive to SEUs, whereas interconnect resources areThe most critical for the device cross section because they use the largest number of configuration bits.
Abstract: This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.
106 citations
"A New Partial Reconfiguration-Based..." refers methods in this paper
...More recently, an analysis that combines the results of radiation testing with those obtained while analyzing the meaning of every bit in the FPGA’s configuration memory was published in [10], [ 11 ]....
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...Following the methodology we presented in [ 11 ], we investigated each injected SEU that provoked fault escaping both the TMR and X-TMR hardening techniques and we correlated them to the classification described in the Section II.B....
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TL;DR: A new analytical approach is described to estimate the dependability of TMR designs implemented on SRAM-based FPGAs that is able to predict the effects of single event upsets with the same accuracy of fault injection but at a fraction of the fault-injection's execution time.
Abstract: In order to deploy successfully commercially-off-the-shelf SRAM-based FPGA devices in safety- or mission-critical applications, designers need to adopt suitable hardening techniques, as well as methods for validating the correctness of the obtained designs, as far as the system's dependability is concerned. In this paper we describe a new analytical approach to estimate the dependability of TMR designs implemented on SRAM-based FPGAs that, by exploiting a detailed knowledge of FPGAs architectures and configuration memory, is able to predict the effects of single event upsets with the same accuracy of fault injection but at a fraction of the fault-injection's execution time.
104 citations
"A New Partial Reconfiguration-Based..." refers background in this paper
...rors depending on the kind of PIP involved [12]....
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TL;DR: In this article, the authors provide the first extensive study of various configuration memories used in programmable devices and explore the interplay between device scaling, process, bias voltage, design, and architecture.
Abstract: Manufacturers of field programmable gate arrays (FPGAs) take different technological and architectural approaches that directly affect radiation performance. Similar technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices' total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.
102 citations
"A New Partial Reconfiguration-Based..." refers background in this paper
...904080 Several radiation tests [2]–[4] have been done to investigated...
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16 Feb 2004
TL;DR: This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory, and describes a method for obtaining the same result with similar devices.
Abstract: This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools dealing with the device configuration memory, we were able to make hypothesis on the meaning of every bit in the configuration memory. From the other side, radiation testing was exploited to validate the hypothesis and to gather experimental evidence about the correctness of the obtained results. As a major result, we can provide detailed information about the effects of SEUs affecting the configuration memory of a commercial FPGA device. As a second contribution, we describe a method for obtaining the same result with similar devices. Finally, the obtained results are crucial to allow the possible usage of SRAM-based FPGAs in safety-critical environments, e.g., by working on the place and route strategies of the supporting tools.
94 citations