A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters
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...not improve the DNL, as confirmed by SMM DACs in [10], [12], [13]....
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Cites background from "A new technique for on-chip error e..."
...While amplitude calibration has been extensively studied [25]–[30], timing calibration has received less attention, especially when...
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Cites background from "A new technique for on-chip error e..."
...I. INTRODUCTION E MERGING wireless and wireline communication stan-dards exploiting wideband and multicarrier modulation, e.g., in base stations, demand lower signal distortion and noise to improve signal quality and system capacity....
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Cites background from "A new technique for on-chip error e..."
...17(b) that if the dual-calibration scheme is applied element wise, instead of row-wise to the DAC, it results in a better INL reduction (similar performance as the switching schemes in [14] and [15]), but at the expense of algorithmic complexity, which now increases to O(n2)....
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"A new technique for on-chip error e..." refers background in this paper
...The errors due to random mismatch can be reduced by increasing the area of the sources [1]....
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...Since is inversely proportional to the square root of the area [1], the area of the upper segment current sources can be reduced by a factor of four....
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