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Journal ArticleDOI

A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters

TL;DR: A novel technique for estimation of DNL based on a step-size measurement is proposed, which greatly reduces the linearity and dynamic range requirements of the measuring circuits.
Abstract: In this paper, we propose a reconfigurable current-steering digital-to-analog converter (DAC). The differential nonlinearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). We propose a novel technique for estimation of DNL based on a step-size measurement. This greatly reduces the linearity and dynamic range requirements of the measuring circuits. A 10-b segmented DAC, along with the associated circuits for DNL estimation and reconfiguration, was designed using 0.35-/spl mu/m CMOS technology and fabricated through Europractice. The paper includes theoretical analysis, simulation, and experimental results for the proposed technique.
Citations
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Journal ArticleDOI
TL;DR: By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range.
Abstract: This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range. Compared to traditional current source calibration techniques and static-mismatch mapping, DMM can reduce the distortion caused by both amplitude and timing mismatch errors. Compared to dynamic element matching, DMM does not increase the noise floor since the distortion is reduced, not randomized. The DMM DAC was implemented in a 0.14 μm CMOS technology and achieves a state-of-the-art performance of SFDR >; 78 dBc, IM3 <; -83 dBc and NSD <; -163 dBm/Hz in the whole 100 MHz Nyquist band.

87 citations


Cites background from "A new technique for on-chip error e..."

  • ...not improve the DNL, as confirmed by SMM DACs in [10], [12], [13]....

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Journal ArticleDOI
TL;DR: To minimize frequency-dependent amplitude and phase errors in the output summing node, which can dominate linearity performance at GHz and mm-wave frequencies, a vertically stacked tree (VST) and feed-forward (FF) path are proposed.
Abstract: A dc-20-GHz multiple-return-to-zero digital-to-analog converter (DAC) is proposed for direct radio frequency synthesis. To minimize frequency-dependent amplitude and phase errors in the output summing node, which can dominate linearity performance at GHz and mm-wave frequencies, a vertically stacked tree (VST) and feed-forward (FF) path are proposed. While the VST minimizes variation in frequency response among the MSB cells, the FF path improves matching between the MSBs and LSBs, providing up to 21-dB improvement in simulated spurious-free dynamic range (SFDR) at 20 GHz. To account for additional errors introduced by process variation, the DAC utilizes per-cell calibration of both amplitude and timing. The DAC is implemented in a 0.13- $\mu \text{m}$ SiGe process with an area of 6.25 mm2 and consumes 1.91 W. After amplitude and timing calibration, >48-dB SFDR and lesser than −46 dBc intermodulation distortion are achieved from dc to 20 GHz.

23 citations


Cites background from "A new technique for on-chip error e..."

  • ...While amplitude calibration has been extensively studied [25]–[30], timing calibration has received less attention, especially when...

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Proceedings ArticleDOI
16 Jun 2010
TL;DR: A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented, which reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty.
Abstract: A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14µm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band.

15 citations


Cites background from "A new technique for on-chip error e..."

  • ...I. INTRODUCTION E MERGING wireless and wireline communication stan-dards exploiting wideband and multicarrier modulation, e.g., in base stations, demand lower signal distortion and noise to improve signal quality and system capacity....

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Journal ArticleDOI
TL;DR: A dual-calibration technique to improve the matching accuracy of digital-to-analog converter (DAC) elements and improve nonlinearity induced static errors in a current-steering thermometer DAC is proposed.
Abstract: In this paper, we propose a dual-calibration technique to improve the matching accuracy of digital-to-analog converter (DAC) elements and improve nonlinearity induced static errors in a current-steering thermometer DAC. The novelty of the proposed dual-calibration scheme lies in obtaining best samples from the error distribution using redundancy for improved matching followed by adaptively reordering these samples to reduce error accumulation. This technique exploits the 2-D nature of the DAC to achieve lower calibration time. We consider the statistical basis for each of these methods and demonstrate statistical modeling of the proposed technique. We demonstrate a 38% reduction in differential nonlinearity (DNL) and 55% reduction in integral nonlinearity (INL) through simulations. We fabricated an 8-bit current steering thermometer DAC in Taiwan Semiconductor Manufacturing Company 65-nm CMOS process. With only 2 redundant cells per row, we show an improvement of 36% in DNL and 50% in INL from the measurement of 16 chips over the baseline DAC.

9 citations


Cites background from "A new technique for on-chip error e..."

  • ...17(b) that if the dual-calibration scheme is applied element wise, instead of row-wise to the DAC, it results in a better INL reduction (similar performance as the switching schemes in [14] and [15]), but at the expense of algorithmic complexity, which now increases to O(n2)....

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References
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Journal ArticleDOI
TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Abstract: The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >

3,121 citations


"A new technique for on-chip error e..." refers background in this paper

  • ...The errors due to random mismatch can be reduced by increasing the area of the sources [1]....

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  • ...Since is inversely proportional to the square root of the area [1], the area of the upper segment current sources can be reduced by a factor of four....

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Journal ArticleDOI
01 Nov 1996
TL;DR: In this article, a delay-locked loop (DLL) and phase-locked loops (PLL) designs based upon self-biased techniques are presented, which achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and low input tracking jitter.
Abstract: Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.

1,006 citations

Book
12 Dec 2017
TL;DR: In this paper, a reference handbook of statistical tables developed to aid in the investigation and solution of many of today's challenging problems is presented, with a focus on the needs of practitioners of statistics.
Abstract: Practicing statisticians and scientists working in diverse fields need an authoritative reference handbook of statistical tables developed to "aid" in the investigation and solution of many of today's challenging problems. This book has been compiled and arranged to meet the needs of these users of statistics.

450 citations

Journal ArticleDOI
Chi-Hung Lin1, Klaas Bult1
TL;DR: In this paper, a 10-b current steering CMOS digital-to-analog converter (DAC) with optimized performance for frequency domain applications is described, where the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist.
Abstract: A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-/spl mu/m, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm/sup 2/. When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry.

389 citations