A Novel 2-Bit/Cell p-Channel Logic Programmable Cell With Pure 90-nm CMOS Technology
22 Jul 2008-IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers)-Vol. 29, Iss: 8, pp 938-940
TL;DR: In this paper, a p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic nonvolatile memory (NVM) applications.
Abstract: A new p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic nonvolatile-memory (NVM) applications. A 0.296-mum2/bit (~35 F2) OTP cell, i.e., 0.592 mum2/cell, with a self-aligned nitride storage node was fabricated using standard 90-nm CMOS processes and is fully independent of gate oxide for high scalability. Additionally, the ultrahigh-density OTP cell exhibits excellent retention, immunity against disturbance, and a wide on/off window under the band-to-band hot electron programming. In summary, the new p-channel OTP cell is a very promising solution for use in high-density logic NVM applications beyond the 90-nm technology node.
Citations
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29 Jan 2014TL;DR: In this article, a nonvolatile memory (NVM) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain is presented.
Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.
21 citations
TL;DR: In this paper, the authors proposed a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications.
Abstract: This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 mum2. This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 A, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node.
14 citations
Cites background from "A Novel 2-Bit/Cell p-Channel Logic ..."
...of the nitride-based memory compared with the floating gate is another significant solution and choice [5]–[8], [11]–[17]....
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...The electron retention of the erase state was studied in [5]–[8]; the nitride of the SAN cell also has a good performance for electron retention....
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...charge redistribution [5]–[8] was also observed during the first 24 h of retention backing, as shown in Fig....
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...Therefore, a great desire for high-density and low-power logic NVM solutions exists [2]–[8]....
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...EMBEDDED nonvolatile memories (NVMs) have received extensive attention in recent years as the demand for customized code storage and circuit trimming has grown [1]–[8]....
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01 Dec 2014
TL;DR: In this article, a self-recovery self-aligned-nitride (SAN) memory cell is proposed and fabricated in 28nm high-k metal gate (HKMG) CMOS process for high-density logic NVM applications.
Abstract: A new saw-like self-recovery Self-Aligned Nitride (SAN) memory cell is proposed and fabricated in 28nm high-k metal gate (HKMG) CMOS process for high-density logic NVM applications. The cell is operated with Source-Side Injection (SSI) for programming and band-to-band hot holes (BBHH) for erasing. Two effective self-heating recovery mechanisms are proposed and performed to maintain a stable On/Off read window after cycling stresses. Besides, the characteristic and reliability comparison of the SAN cell in other technology nodes, 90nm/45nm/32nm, are characterized to further verify the saw-like self-detrapping and self-recovery operation. The new 28nm HKMG SAN memory cell with the self-detrapping recovery results excellent and superior endurance performance and can provide a very promising solution for logic NVM in advanced technologies.
12 citations
23 Apr 2012
TL;DR: In this paper, a 32nm MTP cell with a nitride-based storage node using 32nm strained Si process is demonstrated with an ultra small cell size of 0.0528µm2 by a 32-nm strained-CMOS fully logic compatible process.
Abstract: A 32nm MTP cell with a nitride-based storage node using 32nm strained Si process are demonstrated with an ultra small cell size of 0.0528µm2 by a 32nm strained-CMOS fully logic compatible process. A self-aligned tiny nitride storage node is placed in the narrow spacing of two 32nm transistors by a merged transistor spacer mingled with a strained nitride of 32nm strained Si process. The twin-gate cell uses the source side injection (SSI) to obtain 100 times of on/off window by a low program voltage of 3.5V within 1msec. A good reliability in retention and disturb is exhibited due to the inherently decoupling of storage node and transistor gate oxide in this cell, even when gate oxide is thinner than 16A with 32nm gate length only.
6 citations
TL;DR: In this article, a new static RAM (SRAM) cell featuring self-matching characteristic for enhanced static noise margin (SNM) in lowvoltage applications is reported.
Abstract: This paper reports a new static RAM (SRAM) cell featuring its self-matching characteristic for enhanced static noise margin (SNM) in low-voltage applications. This new SRAM employs trimming devices replacing pull-down transistors to compensate mismatches. Through a blanket trimming operation enabling self-matching of the two branches, effective suppression of variability with improved SNM distribution has been successfully demonstrated in nanoscaled SRAMs.
5 citations
References
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TL;DR: In this paper, a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation is presented, which is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction.
Abstract: This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250/spl deg/C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 /spl mu/m process, the area of a bit is 0.315 /spl mu/m/sup 2/ and 0.188 /spl mu/m/sup 2/ in 0.25 /spl mu/m technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications.
1,170 citations
"A Novel 2-Bit/Cell p-Channel Logic ..." refers background in this paper
...The local storage of charge in nitride substantially facilitates the formation of a 2-bit/cell OTP SAN cell [8], and the charges are stored near the PG side or the SG side....
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04 Sep 2007
TL;DR: A new fully CMOS process compatible anti-fuse device with programmable contact with the capability to adapt multiple programmable contacts for the needs of elevated data writing and reading performance.
Abstract: A new fully CMOS process compatible anti-fuse device with programmable contact has been developed for advanced programmable logic applications. This anti-fuse processed by pure logic process and decoupled with transistor gate oxide has a highly stable and extremely wide on/off window. It exhibits superior disturb immunity in program and read operations. The device additionally provides the capability to adapt multiple programmable contacts for the needs of elevated data writing and reading performance. This novel anti-fuse cell is a very promising programmable logic solution with fully CMOS logic compatible process below 0.13?m node.
70 citations
TL;DR: In this article, a three-transistor (3-T) cell CMOS one-time programmable (OTP) ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized.
Abstract: A three-transistor (3-T) cell CMOS one-time programmable (OTP) ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high-voltage blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option of high-density CMOS OTP ROM array for modern digital as well as analog circuits.
52 citations
"A Novel 2-Bit/Cell p-Channel Logic ..." refers methods in this paper
...The reliable storage mechanism makes this SAN cell highly scalable and compatible with an advanced CMOS process, which used to constrain cell scaling associated with other OTP solutions [6], [7]....
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08 Apr 1997
TL;DR: In this article, the reliability of a new amorphous silicon/dielectric antifuse is characterized and modeled, where both breakdown and leakage criteria are used to investigate their effects on time-to-fail.
Abstract: The reliability of a new amorphous silicon/dielectric antifuse is characterized and modeled. Unprogrammed antifuse leakage and time-to-breakdown are functions not only of applied voltage but also of stressing polarity and temperature. Both breakdown and leakage criteria are used to investigate their effects on time-to-fail. A thermal model incorporates the effects of programming and stress currents, ambient temperature, and variation of antifuse resistance with temperature. The measured temperature dependence of antifuse resistance is used for the first time to derive key physical parameters in the model.
39 citations
"A Novel 2-Bit/Cell p-Channel Logic ..." refers methods in this paper
...The reliable storage mechanism makes this SAN cell highly scalable and compatible with an advanced CMOS process, which used to constrain cell scaling associated with other OTP solutions [6], [7]....
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15 Nov 2004
TL;DR: In this article, the authors present results on an integrated radiation-hardened technology, which consists of scaled siliconoxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory (NVSM) and bulk CMOS devices designed specifically for high-density, 1 Mb EEPROMs operating in space and military environments.
Abstract: We present recent results on an integrated radiation-hardened technology, which consists of scaled silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory (NVSM) and bulk CMOS devices - devices designed specifically for high-density, 1 Mb EEPROMs operating in space and military environments. These devices operate at low-voltage (+7V, 2.5 ms write, -7V, 7.5 ms erase) with 10-year retention at 150C and greater than 10/sup 5/ erase/write cycles. We describe erase/write, retention and endurance results over a 22-250C temperature range with a tunnel oxide of 1.8 nm, 'oxynitride' of 6.5 nm, and a blocking or 'cap' oxide of 3.0 nm. These scaled SONOS devices exhibit an extrapolated 10-year memory window of 1.2V (22C) and acceptable 0.3V (150C). A SONOS retention model is presented, which includes charge loss from both direct tunneling and thermal excitation. We discuss recent results of a radiation-hardened 1Mb SONOS EEPROM and its memory cell. In addition, we discuss experiments on 'localized' charge storage with hot electron injection to write SONOS/NROM/spl trade/ memory devices for higher functional density with increased retention.
25 citations
"A Novel 2-Bit/Cell p-Channel Logic ..." refers methods in this paper
...The technology computeraided design simulation also indicates that the new reverse reading sequence can yield a wider on/off window [9] whose...
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