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Proceedings ArticleDOI

A novel approach for constrained via minimization problem in VLSI channel routing

16 Mar 2015-pp 145-149

TL;DR: This paper presents a procedure to find out non essential vias in CVM problem and shows the experimental results and hardcopy solutions of some layout to prove that this approach obtains better results compared to conventional algorithms.
Abstract: Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.
Citations
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Journal Article
Abstract: Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

4 citations


References
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Journal ArticleDOI
Chi-Ping Hsu1Institutions (1)
TL;DR: This paper describes the topological routing algorithm in detail, based on a circle graph representation of the net intersection information of the routing problem, which selects a maximal set of nets that can be routed without vias.
Abstract: A new approach to the two-dimensional routing utilizing two layers is proposed. It consists of two major steps, topological routing and geometrical mapping. This paper describes the topological routing algorithm in detail. Based on a circle graph representation of the net intersection information of the routing problem, a maximal set of nets that can be routed without vias are selected. The layer assignments for the selected nets are determined by a global analysis so that the total number of vias needed is minimum. The layer assignment problem turns out to be a maximum-cut problem on an edge-weighted graph and we developed a greedy algorithm for it. According to the layer assignments, the detailed topological routes are then generated.

101 citations


Journal ArticleDOI
Malgorzata Marek-Sadowska1Institutions (1)
TL;DR: It is shown that the simplest problem of this type is NP-complete and a heuristic algorithm for topological via minimization is proposed and proposed.
Abstract: Based on graph theory, a study of via minimization problem is presented. We show that the simplest problem of this type is NP-complete and propose a heuristic algorithm for topological via minimization.

85 citations


Journal ArticleDOI
Majid Sarrafzadeh1, Der-Tsai Lee1Institutions (1)
TL;DR: A two-chain maximum dominance problem, which is of interest in its own right, is considered, and its applications to other very large-scale integration layout problems are shown.
Abstract: A topological via minimization problem in a two-layer routing environment is examined. The problem of minimizing the number of vias needed to route n two-terminal nets in a bounded routing region is shown to be NP-hard. However, in the case of a two-shore routing region, the topological via minimization problem can be solved in O(n/sup 2/ log n) time. As a basis for the algorithm, a two-chain maximum dominance problem, which is of interest in its own right, is considered, and its applications to other very large-scale integration layout problems are shown. >

74 citations



Journal ArticleDOI
Gopal1, Coppersmith, WongInstitutions (1)
TL;DR: This paper considers the problem of local wiring in a VLSI chip and is able to find polynomial time optimal algorithms while, for others, it proves NP-completeness and suggest efficient heuristics.
Abstract: In this paper we consider the problem of local wiring in a VLSI chip. The problem is one of interconnecting two sets of terminals, one set on each side of a wiring channel, in accordance with a given interconnection pattern, and to accomplish this while minimizing some objective function. We make the further assumption that the terminals are not rigidly positioned and can be "moved" provided that this does not change the structural intent of the circuit. Several objective functions are considered-channel width, channel length, channel area, channel perimeter, number of via holes, as well as some constrained objective functions. For some of these objective functions, we are able to find polynomial time optimal algorithms while, for others, we prove NP-completeness and suggest efficient heuristics.

52 citations


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19991