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Proceedings ArticleDOI

A novel approach for constrained via minimization problem in VLSI channel routing

16 Mar 2015-pp 145-149
TL;DR: This paper presents a procedure to find out non essential vias in CVM problem and shows the experimental results and hardcopy solutions of some layout to prove that this approach obtains better results compared to conventional algorithms.
Abstract: Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.
Citations
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Journal Article
TL;DR: In this article, a new approach is proposed for two-layer VLSI routing, which is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.
Abstract: Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

4 citations

References
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Journal ArticleDOI
TL;DR: In this article, the constrained via minimization problem for VLSI three-layer routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized.
Abstract: The constrained via minimization problem for VLSI three-layer routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. This problem has been shown to be NP-complete 15 . In this paper, this problem is first transformed to the contractibility problem of a three-colourable graph, then an heuristic algorithm is proposed on the basis of the graph contractability model. From experimental results, the algorithm proves faster and more efficient at generating very good results. For a typical case, the number of vias can be reduced by about 30%.

16 citations

Proceedings ArticleDOI
18 Jan 1999
TL;DR: A new approach is proposed for two-layer VLSI routing that is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.
Abstract: Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

16 citations

Proceedings ArticleDOI
02 Jul 1986
TL;DR: This procedure can be used as a preprocessor for the algorithms for CVM problems and shows that the procedure is efficient and can identify most of essential vias.
Abstract: The objective of the via minimization is to assign wire segments into different layers to minimize the number of vias required. Several algorithms have been proposed for the Constrained Via Minimization (CVM) problem where the topology of the given layout is fixed. In a CVM problem, some vias may be "essential" to the given layout. That is, they have to be selected and cannot be replaced by other vias. In this paper we present a procedure to find most of the essential vias. This procedure can be used as a preprocessor for the algorithms for CVM problems. Experimental results show that the procedure is efficient and can identify most of essential vias.

12 citations

Proceedings ArticleDOI
01 May 1990
TL;DR: A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing and it is shown that the algorithm is fast and efficient, thus generating very good results.
Abstract: Via minimization is the same as the layer assignment problem in VLSI or PCB routing. It consists of determining which layers can be used for routing the wire segments such that the number of vias can be minimized. A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing. Some associated constraints, such as restricted terminals and adjacent limitation, are addressed extensively. According to the results, the algorithm is fast and efficient, thus generating very good results. >

11 citations

Proceedings ArticleDOI
H. Kim1
05 Apr 1990
TL;DR: It is shown that the problem of via minimization in VLSI routing with movable terminals can be solved in O(n log n) time by using the algorithm finding a maximum independent set in a permutation graph.
Abstract: It is shown that the problem of via minimization in VLSI routing with movable terminals can be solved in O(n log n) time by using the algorithm finding a maximum independent set in a permutation graph. It is also shown that the nets of an example are routed with fewer tracks and vias. Therefore, the number of vias is reduced by using a correct algorithm rather than an algorithm finding a length of largest up-sequence. >

5 citations