Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.

Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

A novel approach for constrained via minimization problem in VLSI channel routing

An efficient approach to constrained via minimization for two-layer VLSI routing

An algorithm for three-layer channel routing with via minimization is presented. It aims at minimizing both the number of vias and the number of tracks. The algorithm has been coded in Pascal and implemented on an XT/286 computer. Experimental results show that, compared with HVH routing, the numbers of vias are decreased by about 40-50% and, for some examples, the numbers of tracks are also less than those of known results. Besides, the routability is 100% regardless of whether there exists a cycle vertical constraint or not. >

An algorithm for three-layer channel routing with via minimization

Hopfield neural networks (HNN) and simulated annealing (SA) are two recent approaches to solving many combinatorial optimization problems. But, the disadvantages of HNN are that it can often converge at local minimum and the quality of solutions depends on the initial state because of sensitivity of parameterization. On the other hand, SA is designed to cope with the problem of convergence to a local minimum. SA, however, requires unacceptably large computing time. So, a new algorithm called mean field annealing (MFA) which can be interpreted as a generalization of HNN, is applied to optimization problems efficiently. In this paper, we propose a new approach based on MFA to solving of the minimization problem. Also we show that our approach can be applied to multi-layer as well as two-layer routing, and optimal solutions can be obtained by properly adjusting the parameter in the given energy function.

A novel approach for constrained via minimization problem in VLSI channel routing

Citations

An efficient approach to constrained via minimization for two-layer VLSI routing

References

An algorithm for three-layer channel routing with via minimization

A new approach to via minimization problem in VLSI chip design

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