A Novel Approach to Improve the Performance of Charge Plasma Tunnel Field-Effect Transistor
01 Jan 2018-IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 65, Iss: 1, pp 282-289
TL;DR: In this article, a distinct approach for realizing charge plasma tunnel field effect transistor (CP TFET) was presented, where p+ substrate is taken as silicon film and then metal electrodes with specific work functions are deposited over the silicon film to accumulate n+ drain and intrinsic channel regions.
Abstract: A distinct approach is presented for realizing charge plasma tunnel field-effect transistor (CP TFET) wherein p+ substrate is taken as silicon film and then metal electrodes with specific work functions are deposited over the silicon film to accumulate n+ drain and intrinsic channel regions. This creates abruptness and reduces the barrier at the source/channel interface of CP TFET, which improves the dc characteristics of the device. Furthermore, the drain electrode is separated into two sections and applied with dual work function, which reduces the ambipolar behavior, parasitic capacitance, and enhances radio frequency parameters. The crux of the script is to advance the performance of the device while maintaining the classical CMOS fabrication flow with its inherent advantages by using p+ substrate initially. To analyze the performance, a comparison between conventional CP TFET and dual drain electrode CP TFET (proposed) is shown at the simulation level. Optimization of length and workfunction of the section of drain electrode adjacent to the channel is demonstrated to assess the desired ON-current and ambipolarity of the device. Furthermore, the device performance is examined with the application of multigate work function and heterogate dielectric engineering to achieve more improvements in device performance.
Citations
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TL;DR: In this paper, the authors proposed a DLTFET with an oversized back gate (OBG) that effectively suppresses ambipolar behavior even upto gate voltage, which has been reported to degrade the tunneling phenomenon at gate-source interface.
Abstract: Tunnel field-effect transistors (TFETs) have shown attractive device performance making them a potential candidate to replace MOSFETs in future technologies. However, the inherent ambipolar characteristic of TFETs poses challenge in digital applications. The gate–drain overlap in conventional TFETs efficiently suppresses the ambipolar conductivity. On the other hand, in dopingless TFETs (DLTFETs), due to the requirement of separate gate and drain electrodes for electrostatically creating doped and intrinsic regions, gate–drain overlap cannot be realized. However, gate–drain overlap can be effectively realized using oversized back gate (OBG). Therefore, in this paper, we have proposed a DLTFET with an OBG that effectively suppresses ambipolar behavior even upto gate voltage ${V}_{\textsf {GS}} = -\textsf {1}$ V. Misalignment study is also performed for the gate length ${L}_{G} = \textsf {20}$ nm which has been reported to degrade the tunneling phenomenon at gate–source interface. It is observed that the proposed device is more tolerant to misalignment due to its OBG. The OBG also provides improvement in ${I}_{\textsf {on}}$ ( $\sim 1.4\times $ ) due to enhanced band bending at gate–source interface. To demonstrate the advantage of proposed device architecture over existing architectures, we compare the performance of proposed device with other existing techniques such as dual material gate and dual material drain architectures. The OBG-DLTFET has shown better ambipolar and on-state characteristics in comparison to the existing techniques.
37 citations
Cites background from "A Novel Approach to Improve the Per..."
...Various techniques, such as the use of different channel materials [15], hetrodielectric [12], dual metal gate [6], asymmetric dual-k spacers [16], and metal layer DLTFET (ML-DLTFET) [17], [18], have been proposed to enhance the ON-state current....
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...Another novel way to form the TFET p-i-n structure on the p+ substrate has also been proposed, which eliminates the need of spacer between gate and source [6]....
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TL;DR: In this paper, an In0.53Ga0.47As/In0.52Al0.48As heterojunction dopingless tunnel field effect transistor (HDL-TFET) with an HfO2/SiO2 heterogate dielectric is proposed, where the N+-pocket with variable electron concentration can be formed by adjusting the length of source-side channel (LSC) based on the charge plasma concept, instead of employing conventional ion implantation or dual-material gate techniques.
Abstract: In this paper, an In0.53Ga0.47As/In0.52Al0.48As heterojunction dopingless tunnel field-effect transistor (HDL-TFET) with an HfO2/SiO2 heterogate dielectric is proposed, where the N+-pocket with variable electron concentration can be formed by adjusting the length of source-side channel (LSC) based on the charge plasma concept, instead of employing conventional ion implantation or dual-material gate techniques. It aims to improve the device performance and simplify the device fabrication. At the drain bias of 0.3 V, numerical simulations show that the on-state current (ION) of the HDL-TFET with LSC = 4 nm can approach ~10−5A/ $\mu \text{m}$ that is far higher than that of the Si-DL-TFET (~10−10A/ $\mu \text{m}$ ), and the average subthreshold swing (SSavg) can approach 36.6 mV/decade that is significantly lower than that of the Si-DL-TFET (89.2 mV/decade). It is also found that the drain-induced barrier lowering (DIBL) effect and the ambipolar current can be effectively suppressed in the HDL-TFET because of an existence of heterojunction. Under the condition of low gate and drain biases, the HDL-TFET exhibits peak values of the cutoff frequency (fT) and the maximum oscillation frequency (fmax) approaching 13 and 4.73 GHz, respectively, while the Si-DL-TFET yields those of 8.05 and 2.26 GHz, respectively, under relatively higher biases. It indicates that the HDL-TFET is a promising device for low-power consumption radio frequency applications.
21 citations
Cites methods from "A Novel Approach to Improve the Per..."
...Novel p-n-i-n TFETs that inserting a thin N+-pocket in the source-side channel (SC) of the conventional TFET have been proposed in the previous publications [7], [8], [20], [21], which can greatly improve vON because the N+-pocket can adjust the energy band profile so as to enhance the lateral electric field and reduce the lateral tunneling distance....
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TL;DR: In this paper, the influence of interface trap charges on the characteristics of asymmetric dielectric modulated dual short gate tunnel field effect transistor (ADMDG-TFET) has been analyzed.
Abstract: In this paper, the influence of interface trap charges on the characteristics of asymmetric dielectric modulated dual short gate tunnel field effect transistor (ADMDG-TFET) has been analyzed. The effect of a donor (positive) and acceptor (negative) trap charges with various concentrations on the device d.c characteristics are studied. A comparative analysis has been performed between symmetric silicon dual gate tunnel field effect transistor (DG-TFET) and ADMDG-TFET (both Si and Si0.3Ge0.7) with matching dimensions in the presence/absence of interface trap charges. It is found that a shift in threshold voltage (Vth) and subthreshold swing (SS) degradation are observed due to the presence of interface traps in both devices. However, the ADMDG TFET is more immune to Vth shift and SS degradation by acceptor and donor interface traps compared to silicon DG TFET. Also, the ambipolar current in ADMDG TFET is more suppressed than the silicon DG TFET in the presence of trap charges.
20 citations
TL;DR: In this article, a dual side doping-less (DL) GaAs0.5Sb0·5/In0.53Ga0.47As heterojunction tunnel FET (DDL-HTFET) configuration with hetero-gate-dielectric material (HfO2/SiO2) has been proposed.
19 citations
TL;DR: In this article, a dual-material double gate tunnel field effect transistor (DMDGTFET) with reduced high-K dielectric length and drain electrode thickness was proposed and performed a TCAD simulation.
Abstract: A Dual Material Double Gate Tunnel Field Effect Transistor (DMDGTFET) with reduced high-K dielectric length (LK = 15 nm) and drain electrode thickness (6 nm) is proposed and performed a TCAD simulation. The simulation result of proposed device exhibits suppression in gate-to-drain capacitance (CGD). The (CGD) is proportional to dielectric constant (e) of the gate insulator and drain-electrode thickness of device. In the proposed DMDGTFET, the reduction in drain electrode thickness and LK gives a low electron concentration (Q) and low dielectric constant (e) in channel/drain junction, respectively, which results in suppression of CGD. At VGS = 2 V, the CGD for the proposed and conventional device are 9 f F, and 7 f F, respectively. In addition, the proposed device exhibit unity current-gain cut-off frequency of 62 GHz, while it is 57 GHz for conventional device. The on-current (ION) of the proposed device is also measured as 2 × 10−5 (A/mm). Thus, the proposed DMDGTFET is potential candidate for fast switching applications without compromising on-current (ION).
10 citations
References
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01 Jan 1998
TL;DR: Integrated circuits will lead to such wonders as home computers or at least terminals connected to a central computer, automatic controls for automobiles, and personal portable communications equipment as mentioned in this paper. But the biggest potential lies in the production of large systems.
Abstract: The future of integrated electronics is the future of electronics itself. The advantages of integration will bring about a proliferation of electronics, pushing this science into many new areas. Integrated circuits will lead to such wonders as home computers—or at least terminals connected to a central computer—automatic controls for automobiles, and personal portable communications equipment. The electronic wristwatch needs only a display to be feasible today. But the biggest potential lies in the production of large systems. In telephone communications, integrated circuits in digital filters will separate channels on multiplex equipment. Integrated circuits will also switch telephone circuits and perform data processing. Computers will be more powerful, and will be organized in completely different ways. For example, memories built of integrated electronics may be distributed throughout the machine instead of being concentrated in a central unit. In addition, the improved reliability made possible by integrated circuits will allow the construction of larger processing units. Machines similar to those in existence today will be built at lower costs and with faster turnaround.
9,647 citations
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
"A Novel Approach to Improve the Per..." refers background in this paper
...new device tunnel field-effect transistor (TFET) based on quantum tunneling phenomena has gathered a huge attraction as a competent device due to its ability to provide extremely low OFF-state current (IOFF) and steeper SS [9]–[12]....
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25 Oct 2010
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.
1,389 citations
"A Novel Approach to Improve the Per..." refers background in this paper
...new device tunnel field-effect transistor (TFET) based on quantum tunneling phenomena has gathered a huge attraction as a competent device due to its ability to provide extremely low OFF-state current (IOFF) and steeper SS [9]–[12]....
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TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
"A Novel Approach to Improve the Per..." refers background or methods in this paper
...Extraction of point slope is done similarly as done in [18] for all the devices and shown in the form of bar chart in Fig....
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...BTBT model calculates tunneling rate at each point of the electric field as done in [18], whereas nonlocal BTBT model...
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...The point value of SS is defined as the minimum swing value at any point on the Ids–Vg curve) [18]....
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TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
Abstract: This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.
903 citations
"A Novel Approach to Improve the Per..." refers background in this paper
...Hence, the formation of drain region using dual metal gate can be done easily without affecting it with process variation providing better electrical behavior and cost effectiveness [27]....
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