A Novel Asymmetrical 21-Level Inverter for Solar PV Energy System With Reduced Switch Count
TL;DR: In this article, a novel asymmetric 21-level multilevel inverter topology for solar PV application is presented, where the PV voltage is boosted over the DC link voltage using a three-level DC-DC boost converter interfaced in between the solar panels and the inverter.
Abstract: This article presents a novel asymmetrical 21-level multilevel inverter topology for solar PV application. The proposed topology achieves 21-level output voltage without H-bridge using asymmetric DC sources. This reduces the devices, cost and size. The PV standalone system needs a constant DC voltage magnitude from the solar panels, maximum power point tracking (MPPT) technique used for getting a stable output by using perturb and observe (P&O) algorithm. The PV voltage is boosted over the DC link voltage using a three-level DC-DC boost converter interfaced in between the solar panels and the inverter. The inverter is tested experimentally with various combinational loads and under dynamic load variations with sudden load disturbances. Total standing voltage with a cost function for the proposed MLI is calculated and compared with multiple topologies published recently and found to be cost-effective. A detailed comparison is made in terms of switches count, and sources count, gate driver boards, the number of diodes and capacitor count and component count level factor with the same and other levels of multilevel inverter and found to be the proposed topology is helpful in terms of its less TSV value, devices count, efficient and cost-effective. In both simulation and experimental results, total harmonic distortion (THD) is observed to be the same and is lower than 5% which is under IEEE standards. A hardware prototype is implemented in the laboratory and verified experimentally under dynamic load variations, whereas the simulations are done in MATLAB/Simulink.
Citations
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TL;DR: In this paper , a new single-phase asymmetrical multilevel inverter (MLI) that can generate 33 levels at the output with fewer components and lower total standing voltage (TSV) at the switches is presented.
Abstract: Multilevel inverters with a high device count, low boosting and DC voltage imbalance are all common problems exists in the traditional topologies. In this article, a new single-phase asymmetrical multilevel inverter (MLI) that can generate 33 levels at the output with fewer components and lower total standing voltage (TSV) at the switches is presented. The multiple input sources of the proposed inverter make it suited for the use in renewable energy generating systems which have a variety of DC sources. The stress distribution among the switches is investigated that reduces the use of high rated devices with which overall cost of the inverter gets reduced. The topology can be extended by adding the circuits in series for higher levels. The performance of the inverter is calculated considering a variety of critical parameters such as TSV, cost function (CF), power loss, and efficiency calculations. The MLI is tested under dynamic load conditions with sudden load disturbances with a range of combinational loads and it has been determined to be stable throughout its operation. A detailed comparison is made based on stress across the switches, stress distribution, switches count, DC sources count, gate driver circuits, component count factor, TSV, CF, and other existing topologies using graphical representations and shown to be cost-effective and superior in all aspects. The total harmonic distortion (THD) derived from simulation and experiment complies with IEEE standards. The proposed framework has been developed in MATLAB/Simulink and tested in a laboratory environment with hardware.
9 citations
TL;DR: In this paper , the authors proposed two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter.
Abstract: Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.
8 citations
TL;DR: A comprehensive overview of recently developed multilevel inverters and a solution for developing the MLIs for future research on renewable energy applications is provided in this article , where the design and functioning of each topology as well as each group are examined in this study.
8 citations
21 May 2021
TL;DR: In this article, the authors analyze the multilevel inverters (MLI) topologies into two categories which are symmetric and asymmetric configuration which contain the reduced number of switches.
Abstract: Multilevel inverters (MLIs) are extremely influential in renewable energy systems, are used to convert DC power into AC. MLIs are more beneficial in comparison to the two-level conventional inverter in terms of lower total harmonic distortion (THD), lesser electromagnetic interference (EMI), increases the capability of fault tolerance, and are more efficient. The major aspect of this review article is to analyze the recent (MLI) topologies into two categories which are symmetric and asymmetric configuration which contains the reduced number of switches $(\mathrm{N}_{\mathrm{S}\mathrm{W}})$. currently, Researchers have an eye on the using reduced number of components in MLI topologies for lesser voltage stress and high efficiency. Performance parameters such as total standing voltage (TSV), THD, and modulation techniques are briefly discussed in this article. furthermore, the general comparison of these topologies is depicted in tabular & graphical representation based on the required number of switches, number of the gate drivers $(\mathrm{N}_{\mathrm{G}\mathrm{D}})$, Number of dc voltage sources $(\mathrm{N}_{\mathrm{D}\mathrm{C}})$, THD, and the number of level $(\mathrm{N}_{\mathrm{L}})$ that are obtained through the multilevel inverter topologies.
7 citations
References
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TL;DR: Compared to the conventional topologies and other hybrid topologies, the newly introduced multilevel inverter has the ability to maximize the number of voltage levels utilizing lower number of DC voltage sources, integrated bipolar transistor (IGBT) switches and gate drivers.
Abstract: This paper introduces a new hybrid topology of multilevel inverter capable of generating 21-level output voltage. The proposed topology is built using the combination of cross-switched bridge and a conventional full H-bridge. Compared to the conventional topologies and other hybrid topologies, the newly introduced multilevel inverter has the ability to maximize the number of voltage levels utilizing lower number of DC voltage sources, integrated bipolar transistor (IGBT) switches and gate drivers. A low frequency modulation technique is used to generate the ideal multilevel output voltage and gate pulses. Furthermore, the proposed topology is validated by building a hardware prototype and obtaining relevant experimental results. The acquired simulated and experimental results indicate the proper functioning of the proposed hybrid topology along with the compatibility of the applied modulation technique. Normal 0 false false false MS X-NONE X-NONE /* Style Definitions */
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21 citations
23 Apr 2013
TL;DR: In this paper, a novel auxiliary converter is proposed that allows the two split halves of the PV source to be directly connected to the two dc-link capacitors, with each half operating at it's respective Maximum Power Point (MPP).
Abstract: In a conventional grid connection of Photovoltaic (PV) system, a number of PV modules are connected in series and integrated to grid through a conventional two level inverter. Due to the impact of partial shading and module mismatch, such systems have a much lower yield compared to their maximum potential. To address this problem, direct connection of PV source to a three-level diode clamped inverter is considered in this paper, resulting in a single stage power conversion. A novel auxiliary converter is proposed that allows the two split halves of the PV source to be directly connected to the two dc-link capacitors, with each half operating at it's respective Maximum Power Point (MPP). This auxiliary converter can be rated for less power converter compare to the inverter capacity. The unequal MPP voltage of these split PV panels may cause detrimental effect on output current of inverter. To address this power quality issue, a modified switching algorithm is discussed to achieve voltage equalization across the split DC-Links of the multilevel inverter. Though the case of a split PV source (with two halves) has been considered, the proposed scheme is equally valid for a PV array split into more than two parts that may be suitable for a higher level Neutral Point Clamped (NPC) inverter. The proposed auxiliary converter and algorithm are evaluated and verified by simulation in MATLAB-Simulink.
14 citations
TL;DR: The results show that POVR is capable of achieving the desired fixed DC voltages even under varying environmental and load conditions, with a steady 230 V at the output, and at full load, the standalone system successfully delivers 97.21% of the theoretical maximum power.
Abstract: In this paper, a perturb and observe (P&O) based voltage regulator (POVR) and a capacitor compensator (CC) circuit are proposed for the implementation on 31-level asymmetrical switch-diode based multi-level DC-link (MLDCL) inverter. Since the application of MLDCL in a standalone photovoltaic (PV) system requires constant DC voltages from PV panels, the POVR strategy is deployed to regulate the voltage along with the capability to deliver the maximum power at full load. Boost DC-DC converters are used as the interface between the panels and the inverter for the POVR operation. The results show that POVR is capable of achieving the desired fixed DC voltages even under varying environmental and load conditions, with a steady 230 V at the output. At full load, the standalone system successfully delivers 97.21% of the theoretical maximum power. Additionally, CC is incorporated to mitigate voltage spikes at the output when supplying power to inductive loads. It successfully eliminates the spikes and also reduces the total harmonic distortion (THD) of output current and voltage from more than 10% to less than 5%, as recommended in IEEE 519 standard.
12 citations
TL;DR: In this paper, the authors present a calculation assessing the cost-effectiveness of an investment in a photo-voltaic system in a case where such energy is used for transport needs in an average family or company.
11 citations
TL;DR: The proposed module generates maximum 21-level bipolar output voltage with asymmetric sources without H-bridge results in reduction in filter cost and size and can be cascaded for high voltage applications.
Abstract: This paper presents a module for single-phase multilevel inverter topology. The proposed module generates maximum 21-level bipolar output voltage with asymmetric sources without H-bridge. This resu...
10 citations