A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET
04 Jan 2016-pp 312-317
TL;DR: High value of bipolar gain is observed in optimally designed SiGe JL-DGFET transistors, which can be utilized for the improvement of sensing margin in dynamic memories and provide an opportunity for future DRAM design in deep nanometer technology.
Abstract: This paper presents novel capacitor less dynamic random access memory (DRAM) cells through band-gap engineered silicon-germanium (SiGe) junction less double gate field effect transistor (JL-DGFET) using two-dimensional commercial TCAD device simulator. The design window of capacitor less DRAM cell and its operations have been described. We observe hysteresis current-voltage characteristic and steep change in sub-threshold slope (SS) in SiGe JL-DGFET. The correlation between the IDS -- VGS and IDS -- VDS characteristics of the device during different operation of memory cells are discussed. Furthermore, high value of bipolar gain (i.e. s) is observed in optimally designed SiGe JL-DGFET transistors, which can be utilized for the improvement of sensing margin in dynamic memories. The results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology.
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Patent•
20 Nov 2018TL;DR: In this paper, a method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first semiconductor layer, a second semiconductor layers, a third semiconductors layer, and a fourth semiconductes layer on the substrate; forming the metal oxide semiconductor (MOS) transistor on the peripheral region.
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the substrate; forming a thyristor on the cell region; removing the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer on the peripheral region; and forming a metal oxide semiconductor (MOS) transistor on the peripheral region.
Patent•
31 Jan 2019
TL;DR: In this paper, the authors describe a substrate having a cell region and a peripheral region, a thyristor on the cell region; a MOS transistor on the peripheral region; and a shallow trench isolation (STI) between the first STI and the MOS transistors.
Abstract: A semiconductor device includes: a substrate having a cell region and a peripheral region; a thyristor on the cell region; a MOS transistor on the peripheral region; a first shallow trench isolation (STI) between the thyristor and the MOS transistor; and a second STI between the first STI and the MOS transistor. The thyristor further includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region; patterned metal layers in the first semiconductor layer; vertical dielectric patterns on the patterned metal layers; and first contact plugs on the fourth semiconductor layer.
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IBM1
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
1,417 citations
TL;DR: In this paper, the authors describe the simulation of the electrical characteristics of a new transistor concept called the junctionless multigate field effect transistor (MuGFET), which has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversionmode devices with PN junctions at the source and drain.
Abstract: This paper describes the simulation of the electrical characteristics of a new transistor concept called the ‘‘Junctionless Multigate Field-Effect Transistor (MuGFET)”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversion-mode devices with PN junctions at the source and drain. The simulation results indicate that the junctionless MuGFET is a very promising candidate for future decananometer MOSFET applications.
508 citations
TL;DR: In this article, the improvement of sub-threshold slope due to impact ionization is compared between standard inversion-mode multigate silicon nanowire transistors and junctionless transistors.
Abstract: The improvement of subthreshold slope due to impact ionization is compared between “standard” inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope.
220 citations
01 Dec 2007
TL;DR: A new generation of the single transistor floating body DRAM is introduced for the first time, largely based on the bipolar transistor existing in the MOS structure, with high margin, low-power consumption, and scalability.
Abstract: A new generation of the single transistor floating body DRAM is introduced for the first time. The new memory is largely based on the bipolar transistor existing in the MOS structure. The memory's main features are high margin, low-power consumption, and scalability.
212 citations
TL;DR: In this article, a capacitorless one-transistor (1T)-dynamic random access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated.
Abstract: A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude and a write speed within several nanoseconds. The capacitorless 1T DRAM is the most promising technology for high-performance embedded-DRAM large-scale integration.
197 citations