A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach
04 Jan 2016-pp 282-287
TL;DR: This work proposes novel methodology which describes the optimized design prediction of ESD protection device under HBM (Human Body Model) stress condition and shows that spacing optimization effectively elevates It2 by increasing the ballasting behavior and uniformity in current distribution while causing only a marginal increment in parasitic capacitance.
Abstract: This work explores the new ESD (electrostatic discharge) protection design methodology for high speed off-chip communication ICs (Integrated Circuits). We propose novel methodology which describes the optimized design prediction of ESD protection device under HBM (Human Body Model) stress condition. Furthermore, we have discussed the ESD-I/O circuit interaction and improved the ESD circuit robustness by varying the various layout parameters and minimizing the parasitic capacitance of the protection device. Here, GG-NMOS (Gate Grounded NMOS) is taken as an ESD protection device. Moreover, LVDS (Low Voltage Differential Signaling) driver circuit is used as test circuit, where we compared the impact of capacitance due to protection device on circuit performance. The second breakdown triggering current (It2) which can be considered a metric of ESD robustness, is dependent on the drain to gate contact spacing (DCGS). We show that spacing optimization effectively elevates It2 by increasing the ballasting behavior and uniformity in current distribution while causing only a marginal increment in parasitic capacitance.
Citations
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TL;DR: A complete transmitter has been designed using low-voltage differential signaling (LVDS) technology, a new analog technology based on the serial I/O interface data communications, which helps to improve the performance of transmitter and reducing electrostatic discharge issues.
Abstract: In this paper, a complete transmitter has been designed using low-voltage differential signaling (LVDS) technology. It is a new analog technology based on the serial I/O interface data communications. The complete transmitter circuit consists of driver, cascode current mirror circuit, pseudo random binary sequence (PRBS), and electrostatic discharge (ESD) pad. Here, transmitter is designed initially, and its biasing has been done using cascode current mirror. The layout parameter variation approach has been used to design ESD protection circuit for transmitter. An effort was made to reduce the parasitic capacitance and parasitic resistance. It helps to improve the performance of transmitter and reducing electrostatic discharge issues. The complete system has been designed using 0.18 μm CMOS technology at 1.8 V. The data rate of 2 Gbps and power consumption of 6.3 mW has been achieved using Cadence virtuoso PDK of Silatera Malaysia.
6 citations
Cites background from "A Novel Co-design Methodology for O..."
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TL;DR: For the high-voltage 60-V square type pLDMOS, a parasitic SCR np arrangement was added into the outer guard-ring zone and modulated the STI width to investigate the impact of the ESD protection immunity.
Abstract: For the high-voltage 60-V square type pLDMOS, a parasitic SCR np arrangement was added into the outer guard-ring zone and modulated the STI width to investigate the impact of the ESD protection immunity. There are five kinds of STI width such as 15 μm (reference group), $\pmb{20 \mu} \mathbf{m}, \pmb{25\mu} \mathbf{m}, \pmb{30\mu} \mathbf{m,}$ and $\pmb{35 \mu} \mathbf{m}$ . As a parasitic SCR ( $\pmb{np}$ type) modulated in the guard ring, $\mathbf{V}_{\mathbf{t}\pmb{1}}$ does not change significantly, and $\mathbf{V}_{\mathbf{h}}$ tends to increase as the STI width becomes wider. The $\mathbf{V}_{\mathbf{h}}$ parameter has a maximum value of 72. $\pmb{288}\mathbf{V}$ in the STI35 DUT. Meanwhile, the $\mathbf{I}_{\mathbf{t}\pmb{2}}$ values can be higher than the reference group 2.856A in the STI15, STI20, STI30 DUTs, especially as for the STI 30 μm DUT (ESD reliability capability $\mathbf{I}_{\mathbf{t}\pmb{2}}$ increased 36.6% compared with the reference group) and the $\mathbf{V}_{\mathbf{h}}$ can exceed 60-V (no latch-up risk).
References
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01 Jan 1995
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Abstract: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.
539 citations
"A Novel Co-design Methodology for O..." refers background or methods in this paper
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TL;DR: In this paper, the authors present a review of recent development in RF ESD protection circuit design, including mis-triggering, ESD-induced parasitic effects on RFIC performance, and characterization of RF EDS protection circuits.
Abstract: Radio frequency (RF) electrostatic discharge (ESD) protection design emerges as a new challenge to RF integrated circuits (IC) design, where the main problem is associated with the complex interactions between the ESD protection network and the core RFIC circuit being protected. This paper reviews recent development in RF ESD protection circuit design, including mis-triggering of RF ESD protection structures, ESD-induced parasitic effects on RFIC performance, RF ESD protection solutions, as well as characterization of RF ESD protection circuits.
136 citations
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TL;DR: In this article, a mixed-mode ESD protection simulation-design methodology is presented, which involves multiple-level coupling in EDS protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion.
Abstract: On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-/spl mu/m CMOS and BiCMOS processes, are presented.
83 citations
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TL;DR: In this paper, a distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip, which is compatible with high-speed layout guidelines.
Abstract: Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models. The large area of the distributed ESD scheme could limit its application to designs such as distributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss transmission lines in addition to a conventional ESD device.
70 citations
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TL;DR: The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage and hence makes the operation at low supply voltages using a conventional 0.18 mum CMOS technology feasible.
Abstract: This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 mum CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 Omega resistor with an output voltage swing of VOD = 400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm2 and the measured output jitter is sigmarms = 4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load RC time constant.
49 citations
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