Journal ArticleDOI
A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications
Chu Yu,Yi-Ting Liao,Mao-Hsu Yen,Pao-Ann Hsiung,Sao-Jie Chen +4 more
- Vol. 57, Iss: 1, pp 40-40
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TLDR
To eliminate the read-only memories used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works.Abstract:
4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM's) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.read more
Citations
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Journal ArticleDOI
Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems
Chu Yu,Mao-Hsu Yen +1 more
TL;DR: A novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems and formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme.
Journal ArticleDOI
Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications
TL;DR: This work concentrates on the trivial multiplications in the input stage of the IFFT unit and replaces them by the proposed ‘pass-logic’, and the performance improvements of the proposed FFT/IFFT implementation have been analysed.
Book ChapterDOI
Radix-2/4 FFT Multiplierless Architecture Using MBSLS in OFDM Applications
G. Manikandan,M. Anand +1 more
TL;DR: In this paper multiplierless radix-2/4 FFT architecture using MBSLS was proposed, but here constant multiplication is replaced by shift and add structure unit and the memory of the twiddle factor is minimized by increasing the computation speed with the help of Winograd Fourier transform algorithm.
Proceedings ArticleDOI
Design of a low power 64 point FFT architecture for WLAN applications
TL;DR: A Radix-43 based FFT architecture suitable for OFDM based WLAN applications and uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs.
Journal ArticleDOI
An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications
TL;DR: An area-efficient and low power 16-bit word-width 64-point Radix-22 and radix-23 pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband and implementation results show reduction in hardware cost and power consumption.
References
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Proceedings ArticleDOI
Designing pipeline FFT processor for OFDM (de)modulation
Shousheng He,M. Torkelson +1 more
TL;DR: By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized and the area/power efficiency has been enhanced.
Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
TL;DR: This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.