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Proceedings ArticleDOI

A novel method for online in-place detection and location of multiple interconnect faults in SRAM based FPGAs

Kumar1, Mupid1, Ramani1, Kamakoti1 
08 Dec 2003-pp 262-265

TL;DR: A novel method for online in-place detection and location of interconnects faults in SRAM-based FPGA systems that performs run time reconfiguration of LUTs in an attempt to detect and locate the interconnect faults, if any, within the faulty sub-circuit.

AbstractThis paper describes a novel method for online in-place detection and location of interconnects faults in SRAM-based FPGA systems. In safety critical systems like space probes, online checkers report misbehavior of sub-circuits within the system. When one such sub-circuit is reported to misbehave, the algorithm proposed in this paper performs run time reconfiguration (RTR) of LUTs in an attempt to detect and locate the interconnect faults, if any, within the faulty sub-circuit. Even in the subcircuit under test, at any given time, only a small section of the LUTs are used by the testing procedure. In this way the degradation of the application is kept at a minimum. The proposed algorithm is in-place, i.e. it does not alter the routing structure of the application.

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Journal ArticleDOI
TL;DR: The authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.
Abstract: Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

169 citations


"A novel method for online in-place ..." refers methods in this paper

  • ...Efficient methods for testing interconnect faults are presented in [3-4]....

    [...]

Proceedings ArticleDOI
27 Apr 1997
TL;DR: A methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices is proposed and it is demonstrated that a set of only 3 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant.
Abstract: This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.

116 citations


"A novel method for online in-place ..." refers methods in this paper

  • ...Efficient methods for testing interconnect faults are presented in [3-4]....

    [...]

Proceedings ArticleDOI
01 Nov 1997
TL;DR: This paper presents the first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic resolution, based on a new Built-In Self-Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty PLBs.
Abstract: Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance. In this paper we present the first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic resolution. Our approach is based on a new Built-In Self-Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty PLBs. An adaptive diagnostic strategy provides identification of faulty PLBs with a 7% increase in testing time over the complete detection test, and can also be used for manufacturing yield enhancement. We present results showing identification of faulty PLBs in defective ORCA chips.

113 citations


"A novel method for online in-place ..." refers methods in this paper

  • ...An algorithm for location of faulty LUTs is described in [6], which is an extension of [5] and exploits the partial reconfigurability of the system....

    [...]