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Proceedings ArticleDOI

A novel method for online in-place detection and location of multiple interconnect faults in SRAM based FPGAs

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TLDR
A novel method for online in-place detection and location of interconnects faults in SRAM-based FPGA systems that performs run time reconfiguration of LUTs in an attempt to detect and locate the interconnect faults, if any, within the faulty sub-circuit.
Abstract
This paper describes a novel method for online in-place detection and location of interconnects faults in SRAM-based FPGA systems. In safety critical systems like space probes, online checkers report misbehavior of sub-circuits within the system. When one such sub-circuit is reported to misbehave, the algorithm proposed in this paper performs run time reconfiguration (RTR) of LUTs in an attempt to detect and locate the interconnect faults, if any, within the faulty sub-circuit. Even in the subcircuit under test, at any given time, only a small section of the LUTs are used by the testing procedure. In this way the degradation of the application is kept at a minimum. The proposed algorithm is in-place, i.e. it does not alter the routing structure of the application.

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References
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Proceedings ArticleDOI

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TL;DR: In this paper, incremental CAD techniques are described that allow functional recovery of FPGA design configurations in the presence of single or multiple operational faults.
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Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

TL;DR: A hierarchical approach to define a set of FPGA configurations which enable interconnect fault detection and diagnosis is developed, which enables the detection of bridging faults involving intracluster interconnect and extracluster interconnect.
Proceedings ArticleDOI

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TL;DR: A generalized new approach for testing interconnects (for boundary scan architectures) as well as field programmable interconnect chips (FPICs) and the applicability of the proposed approach to FPICs is discussed and evaluated by simulation.
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Incoming inspection of FPGA's

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Fault Location in FPGA-Based Reconfigurable Systems

TL;DR: A new technique for locating faulty Lookup Tables (LUTs) in FPGA-based reconfigurable systems based on pseudo-exhaustive Built-In Self-Test where each configured LUT is tested exhaustively.
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