# A novel power analysis attack resilient adiabatic logic without charge sharing

## Summary (1 min read)

### INTRODUCTION

- The Power Analysis Attacks (PAA) [1] attacks have received the most attention in recent years.
- The strength of the PAA comes from the fact that the power consumption of the cryptographic device depends on the intermediate values processed in it.
- There are various countermeasures that have been proposed in the literature [2] - [10] to protect cryptographic implementations and are employed at the algorithmic level, architecture level, and cell (gate) level.
- SyAL and SQAL are based on Efficient Charge Recovery Logic, ECRL [11] .
- These existing adiabatic logic designs suffer from several shortcomings which will be discussed in section II.

### II. SHORTCOMINGS IN THE EXISTING SECURE ADIABATIC LOGIC DESIGNS

- The existing PAA resistant logic has number of shortcomings.
- There is a large improvement of average energy dissipation for the proposed logic because the input stays 'high' and stable even during the recovery phase of the power-clock thus, allows the full recovery of charge from the power-clock.
- It uses dual evaluation network which helps both the output nodes to discharge to ground during the idle phase of the power-clock.
- Fig. 5 (a) and (b) shows the schematic and the equivalent RC models of the internal nodes of the proposed AND/NAND gate for 4 input combinations during the evaluation phase.
- It can be seen that for each input combination the same capacitance value is charged.

### IV. SIMULATION RESULTS

- Simulations were performed in 'typical-typical' process corner using TSMC 180nm CMOS process at 1.8V power supply.
- It also shows that at 1MHz, the energy consumption of the 2-input gates using proposed logic is greater than SQAL and SyAL and is comparable to CSSAL.
- It also shows that on the basis of %NED and %NSD, the performance of SQAL, SyAL and CSSAL changes with frequency.
- The % NED and % NSD were calculated for 15 random inputs at all simulated frequencies.
- The post-layout simulations were carried out for each of the existing and proposed logic designs.

### V. CONCLUSION

- The authors have proposed a novel power analysis attack resilient adiabatic logic which does not require any charge-sharing between the output nodes of the gate.
- The proposed logic completely removes the non-adiabatic losses during the evaluation phase of the power-clock.
- The fullcustom layouts were drawn for the proposed and the existing adiabatic logic.
- The pre-layout and post-layout simulation results show that their proposed logic shows less variation in % NED and % NSD with frequency variations compared to existing adiabatic logic.
- Also their proposed logic exhibits the least value of the % NED and % NSD at all simulated frequencies.

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##### References

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### "A novel power analysis attack resil..." refers background in this paper

...There are several papers that have addressed the design of PAA resilient logic designs such as Sense-Amplifier-Based Logic, SABL [2], Wave Dynamic Differential Logic, WDDL [4], Masked Dual-rail Pre-charge Logic (MDPL) [5], Threephase Dual-rail pre-charged logic (TDPL) [6]....

[...]

...Hiding [2] and masking [3] are amongst the most common countermeasures at the cell level....

[...]

...There are various countermeasures that have been proposed in the literature [2]-[10] to protect cryptographic implementations and are employed at the algorithmic level, architecture level, and cell (gate) level....

[...]

6,757 citations

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### "A novel power analysis attack resil..." refers background in this paper

...There are several papers that have addressed the design of PAA resilient logic designs such as Sense-Amplifier-Based Logic, SABL [2], Wave Dynamic Differential Logic, WDDL [4], Masked Dual-rail Pre-charge Logic (MDPL) [5], Threephase Dual-rail pre-charged logic (TDPL) [6]....

[...]

609 citations

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