scispace - formally typeset
Proceedings ArticleDOI

A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection

Reads0
Chats0
TLDR
A scheme SECURE_IP, which relies on the application of cryptographic principles and the watermarking techniques to provide both direct and indirect IP protection in VLSI physical design, makes unauthorized disclosure of a valuable design infeasible during its transmission, and can easily detect any alteration of the design file during transmission.
Abstract
The emerging trend of design reuse in VLSI circuits poses the threat of theft and misappropriation of intellectual property (IP) of the design. Protection of design IP is a matter of prime concern today. We propose a scheme SECURE_IP, which tackles the problem from an entirely new viewpoint. It relies on the application of cryptographic principles and the watermarking techniques to provide both direct and indirect IP protection in VLSI physical design. It makes unauthorized disclosure of a valuable design infeasible during its transmission, and can easily detect any alteration of the design file during transmission. The proposed scheme ensures authentication of the original designer as well as non-repudiation between the designer (seller) and the buyer. Illegal reselling can be efficiently detected by the proposed scheme. The algorithm SECURE_IP is tested on random and MCNC benchmark instances, and the experimental results are quite encouraging

read more

Citations
More filters
Journal ArticleDOI

SoC: a real platform for IP reuse, IP infringement, and IP protection

TL;DR: The IP-based SoC design flow is discussed to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringement.
Proceedings ArticleDOI

An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based locking

TL;DR: The proposed scheme makes unauthorized disclosure of valuable design almost infeasible, and can easily detect any alteration of the design file during transmission, and ensures authentication of the original designer as well as non-repudiation between the seller and the buyer.
Journal Article

A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test

TL;DR: The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence Pc and higher coverage rate of watermark detection by comparing with the existing methods.
Proceedings ArticleDOI

Encoding of Floorplans through Deterministic Perturbation

TL;DR: The idea of an alternate efficient approach of encoding by deterministic perturbation of design IP resulting in a degraded design of negligible IP value, is proposed here to ensure security during design storage or transmission.
References
More filters
Journal ArticleDOI

Constraint-based watermarking techniques for design IP protection

TL;DR: Watermarking-based IP protection as mentioned in this paper addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch, where a watermark is a mechanism for identification that is nearly invisible to human and machine inspection; difficult to remove; and permanently embedded as an integral part of the design.
Book

An Introduction To VLSI Physical Design

TL;DR: This text treats the physical design of very large scale integrated circuits gradually and systematically with the aim of evaluating the efficiency of automatic design systems through algorithmic analysis.
Journal ArticleDOI

A linear algorithm to find a rectangular dual of a planar triangulated graph

TL;DR: In this article, an O(n)-approximation algorithm was developed to construct a rectangular dual of ann-vertex planar triangulated graphs, where n is the number of vertices.
Proceedings ArticleDOI

Hierarchical watermarking in IC design

TL;DR: A formalization of the watermarking problem is presented and basic algorithms for its generation and detection at several abstraction levels are proposed.
Related Papers (5)