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Journal ArticleDOI

A Novel Trench-Gated Power MOSFET With Reduced Gate Charge

01 Feb 2015-IEEE Electron Device Letters (IEEE)-Vol. 36, Iss: 2, pp 165-167
TL;DR: In this paper, a novel trench power MOSFET structure with a p-n junction in trench to reduce the gate charge is proposed, which exhibits a 495% enhancement in gate-charge.
Abstract: In this letter, we propose a novel trench power MOSFET structure with a p-n junction in trench to reduce the gate charge We utilize the 2-D device simulator, ATLAS, to investigate the characteristics of the proposed structure and compare with the conventional structure As a result, the proposed structure exhibits 495% enhancement in gate-charge $Q_{\mathrm {\mathbf {g}}}$ as compared with the conventional structure, without degrading the other electrical characteristics
Citations
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Journal ArticleDOI
TL;DR: In this article, a method of single-event burnout (SEB) hardening at high linear energy transfer (LET) value range is proposed and investigated by the 2-D numerical simulations.
Abstract: In this article, a method of single-event burnout (SEB) hardening at high linear energy transfer (LET) value range is proposed and investigated by the 2-D numerical simulations. The improved MOSFET using this method and the conventional MOSFET are analyzed and compared to evaluate the effectiveness of this method. Simulation results show that, compared with the conventional MOSFET, the improved MOSFET using this method can effectively and quickly reduce the internal high electric field, thereby reducing the temperature. Under the condition of a LET value of 0.5 pC/ $\mu \text{m}$ and a drain voltage of 1200 V, the maximum drain current is 0.168 A, and the maximum global device temperature is 1724 K, which is much lower than the melting down temperature of silicon carbide (SiC) (3100 K). The hardening method in this article can be applied to different breakdown voltages by adjusting structure parameters.

16 citations


Cites background from "A Novel Trench-Gated Power MOSFET W..."

  • ...gate and drain, then the gate coupling with the drain region is reduced and the gate–drain capacitance is reduced [26]....

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Journal ArticleDOI
06 Oct 2021-Energies
TL;DR: In this paper, an experimental evaluation of GaN FETs in a low voltage electrical drive is carried out, and the experimental investigation is obtained through two different experimental boards to highlight the switching legs' behavior in several operative conditions and different implementations.
Abstract: The efficiency and power density improvement of power switching converters play a crucial role in energy conversion. In the field of motor control, this requires an increase in the converter switching frequency together with a reduction in the switching legs’ dead time. This target turns out to be complex when using pure silicon switch technologies. Gallium Nitride (GaN) devices have appeared in the switching device arena in recent years and feature much more favorable static and dynamic characteristics compared to pure silicon devices. In the field of motion control, there is a growing use of GaN devices, especially in low voltage applications. This paper provides guidelines for designers on the optimal use of GaN FETs in motor control applications, identifying the advantages and discussing the main issues. In this work, primarily an experimental evaluation of GaN FETs in a low voltage electrical drive is carried out. The experimental investigation is obtained through two different experimental boards to highlight the switching legs’ behavior in several operative conditions and different implementations. In this evaluative approach, the main GaN FETs’ technological aspects and issues are recalled and consequently linked to motion control requirements. The device’s fast switching transients combined with reduced direct resistance contribute to decreased power losses. Thus, in GaN FETs, a high switching frequency with a strong decrease in dead time is achievable. The reduced dead time impact on power loss management and improvement of output waveforms quality is analyzed and discussed in this paper. Furthermore, input filter capacitor design matters correlated with increasing switching frequency are pointed out. Finally, the voltage transients slope effect (dv/dt) is considered and correlated with low voltage motor drives requirements.

14 citations

Journal ArticleDOI
TL;DR: In this paper, a new shield gate (SG) trench MOSFET structure was proposed, which utilizes a p-n-doped polysilicon refill as the SG electrode to minimize the total output capacitance or charge.
Abstract: This letter proposes a new shield gate (SG) trench MOSFET structure, which utilizes a p-n-doped polysilicon refill as the SG electrode to minimize the total output capacitance or charge. TCAD simulation is carried out to compare the proposed and conventional device structures. It is shown that the proposed structure offers 30% lower $\text{Q}_{\text {OSS}}$ and 18.2% reduction of inductive switching loss while retaining other attractive characteristics of the SG trench MOSFET.

9 citations


Cites background from "A Novel Trench-Gated Power MOSFET W..."

  • ...[8] theoretically investigated the concept of replacing the active gate electrode with a polysilicon PN junction to reduce the gate charge QGD of the conventional single-gate trench MOSFETs....

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Journal ArticleDOI
TL;DR: It is demonstrated that an 80 V DGT-LDMOS can achieve 2.3 times higher drain current, 6.5 times reduction in specific on-resistance, 86% improvement in peak transconductance, 3 times increase in cut-off frequency, and 3 times improvement in maximum oscillation frequency when compared with 80 V conventional LDMOS.
Abstract: In this paper, we propose a dual-gate trench laterally diffused MOSFET (DGT-LDMOS) on silicon-on-insulator by utilizing trenches in the drift region. The proposed device has one horizontal-gate placed on the surface and another vertical-gate located in a trench. The dual-gate structure creates two channels in p-base which carry drain current in parallel. Another trench filled with oxide is placed in the drift region to enhance the reduced-surface-field effect. Based on two-dimensional simulations, it is demonstrated that an 80 V DGT-LDMOS can achieve 2.3 times higher drain current, 6.5 times reduction in specific on-resistance, 86% improvement in peak transconductance, 3 times increase in cut-off frequency, and 2.3 times improvement in maximum oscillation frequency with 3 times reduction in cell pitch when compared with 80 V conventional LDMOS.

7 citations

Journal ArticleDOI
TL;DR: In this paper, a comprehensive review on the various Power MOSFET structures that have been developed during the past decade is presented and issues related to their performance are analyzed on the basis of following parameters: on-state resistance and breakdown voltage mainly.
Abstract: The paper presents the comprehensive review on the various Power MOSFET structures that have been developed during the past decade. Various structures of Power MOSFET like LDMOS, VDMOS, V-Groove MOS, Trench Gate MOS, FLIMOS, SJ-MOS, and Strained Si MOS are studied and issues related to their performance are analyzed on the basis of following parameters: on-state resistance and breakdown voltage mainly, as trade-off should be maintained between them while designing the structure of Power MOSFET. The on-resistance should be low at high breakdown voltage for enhancing the performance of MOSFET device. keywords: Power MOSFET, On-state resistance, Breakdown Voltage, VDMOS, SJ-MOS.

7 citations


Cites background from "A Novel Trench-Gated Power MOSFET W..."

  • ...5% Switching delay decreases without changing Ron [14] Trench MOS 2010 ] Jacky C....

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References
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Patent
20 Oct 1999
TL;DR: The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.
Abstract: Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower-trench based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.

375 citations

Proceedings ArticleDOI
14 Apr 2003
TL;DR: In this paper, a power trench MOSFET with W-shaped gate structure is presented, which demonstrates a significant reduction in gate-drain charge Qgd, a low on-resistance, and good production process margin.
Abstract: A new power Trench MOSFET with W-shaped gate structure (WMOSFET) that demonstrates a significant reduction in gate-drain charge Qgd, a low on-resistance, and good production process margin is reported. The gate is formed using a thicker oxide at the bottom of the trench that is self-aligned to the P-body/N-epi junction. Fabricated 35 V N-channel devices exhibit a Rdson*Qgd Figure of Merit of 12.5 m/spl Omega/.nC with V/sub GS/=10V and V/sub DD/=15V. Experimental data of devices fabricated using LOCOS and Sub Atmospheric CVD (SACVD) processes to form the thicker oxide layer along with simulation results are presented.

139 citations


"A Novel Trench-Gated Power MOSFET W..." refers background in this paper

  • ...Then the W-shaped gate trench structure [6], [7] is proposed to overcome this drawback....

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Patent
26 Sep 2005
TL;DR: In this article, a double-diffused metal-oxide-semiconductor (DMOS) field effect transistor with an improved gate structure is presented, which includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate.
Abstract: A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

109 citations

Patent
24 Apr 1998
TL;DR: In this article, a DMOS power device supported on a substrate is described, which includes a drain of a first conductivity type disposed at bottom surface of the substrate, a gate disposed in a trench opened from a top surface of substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure.
Abstract: This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure. The double gate-oxide structure includes a thick-oxide-layer covering walls of the trench below an upper portion of the trench and a thin-gate-oxide covering walls of the upper portion of the trench thus defining a champagne-glass shaped gate in the trench. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate surrounding a top portion of the trench. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate surrounding the trench and encompassing the source region.

95 citations

Journal ArticleDOI
TL;DR: In this article, the authors analyzed the switching behavior in power trench MOSFETs by using experiments and simulations, focusing on the charge density Q/sub gd/, which can be used for further optimization of these devices.
Abstract: For the switching performance of low-voltage (LV) power MOSFETs, the gate-drain charge density (Q/sub gd/) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (R/sub ds,on/) and Q/sub gd/ is commonly used for quantifying the switching performance for a specified off-state breakdown voltage (BV/sub ds/). In this paper, we analyzed the switching behavior in power trench MOSFETs by using experiments and simulations, focusing on the charge density Q/sub gd/. The results of this analysis can be used for further optimization of these devices. The results show that the Q/sub d/ can be split into three charge contributions: accumulation, depletion, and inversion charge. It is shown that the inversion charge is located mainly underneath the trench bottom. The accumulation and depletion charge contribute each about 45% in conventional LV trench MOSFETs and can be reduced by using a thick bottom oxide in a shallow trench gate just extending in the drift region. Further, we derived an analytical model for calculating the Q/sub gd/, that takes into account the geometry dependence.

55 citations


"A Novel Trench-Gated Power MOSFET W..." refers methods in this paper

  • ...FOR the power trench MOSFETs (UMOSFETs) used as switching devices or DC-to-DC converters, it is extremely crucial to obtain the higher switching speed by reducing gate-drain charge (Qgd), due to the presence of the trench bottom which makes the gate coupling with drain more than the planar devices [1]–[3]....

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