A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation
TL;DR: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation, which allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling.
Abstract: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I/sub ds/, conductances and their derivatives throughout all V/sub gs/, V/sub ds/, and T/sub bs/, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on.
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TL;DR: In this paper, the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications is examined.
Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.
384 citations
TL;DR: In this paper, the authors describe the latest and most advanced surface potential-based model jointly developed by The Pennsylvania State University and Philips, which includes model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources.
Abstract: This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context
358 citations
TL;DR: In this article, the authors present the basis of the modeling of the MOS transistor for circuit simulation at RF and present a physical equivalent circuit that can be easily implemented as a Spice subcircuit.
Abstract: This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-/spl mu/m CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement.
288 citations
Cites background from "A physical and scalable I-V model i..."
...Although good results can be obtained for lower frequency circuits (typically below 100 MHz), the simulation of RF circuits in the gigahertz frequency range with the available MOS compact models such as BSIM3v3 [13], [14], MOS Model 9 [15], [16], or EKV [17]–[20] without consideration of the…...
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TL;DR: In this article, a simple semi-empirical model ID(VGS, VDS) for short-channel MOSFETs applicable in all regions of device operation is presented.
Abstract: A simple semiempirical model ID(VGS, VDS) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called ldquotop-of-the-barrier-transportrdquo model, and we refer to it as the ldquovirtual sourcerdquo (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage VGS = Vdd); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically Ioff at VGS = 0 V) and at high VDS; 5) total resistance at VDS = 0 V and VGS = Vdd and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection.
198 citations
TL;DR: In this article, an analytic potential model for long-channel symmetric and asymmetric double-gate MOSFETs is presented, which is derived rigorously from the exact solution to Poisson's and current continuity equation without the charge-sheet approximation.
Abstract: This paper presents an analytic potential model for long-channel symmetric and asymmetric double-gate (DG) MOSFETs. The model is derived rigorously from the exact solution to Poisson's and current continuity equation without the charge-sheet approximation. By preserving the proper physics, volume inversion in the subthreshold region is well accounted for in the model. The resulting analytic expressions of the drain-current, terminal charges, and capacitances for long-channel DG MOSFETs are continuous in all operation regions, i.e., linear, saturation, and subthreshold, making it suitable for compact modeling. As no fitting parameters are invoked throughout the derivation, the model is physical and predictive. All parameter formulas are validated by two-dimensional numerical simulations with excellent agreement. The model has been implemented in Simulation Program with Integrated Circuit Emphasis version 3 (SPICE3), and the feasibility is demonstrated by the transient analysis of sample CMOS circuits.
190 citations
Cites methods from "A physical and scalable I-V model i..."
...OMPACT models of MOSFETs have evolved from piecewise models to unified models due to the numerical divergence problems in circuit simulation caused by discontinuous derivatives of MOSFET models [1], [ 2 ]....
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References
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TL;DR: In this paper, a physical model involving the breaking of the ≡ Si s H bonds was proposed to explain the observed time dependence of MOSFET degradation and the observed channel field.
Abstract: Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.
1,029 citations
"A physical and scalable I-V model i..." refers background in this paper
...model [ 12 ], the due to the substrate current induced body effect can be obtained easily...
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...where and are similar to the and parameters given in [ 12 ], and can be extracted experimentally....
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TL;DR: The Berkeley short-channel IGFET model (BSIM) as discussed by the authors is an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design is described.
Abstract: The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.
560 citations
"A physical and scalable I-V model i..." refers methods in this paper
...Some models, including several previous versions of BSIM that have been developed and implemented in SPICE for use in circuit simulation [3]–[5], used separate model expressions for such device operation regimes as subthreshold and strong inversion....
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...Separate expressions for channel charge density in strong inversion and subthreshold regions at small were used in previous BSIM models as follows [3]–[5]:...
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TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >
466 citations
"A physical and scalable I-V model i..." refers methods in this paper
...is the threshold voltage of the device and is given as follows [9], [10]:...
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09 May 1993
TL;DR: The requirements for good MOSFET modeling as they apply to usage in analog and mixed analog-digital design are discussed, and it is argued that most CAD models today fail tests even for simple, long-channel devices at room temperature.
Abstract: The requirements for good MOSFET modeling are discussed, as they apply to usage in analog and mixed analog-digital design. A set of benchmark tests that can be easily performed by the reader are given, and it is argued that most CAD models today cannot pass all the tests, even for simple, long-channel devices at room temperature. A number of other problems are discussed, and in certain cases specific cures are suggested. The issue of parameter extraction is addressed. Finally, the context of model development and usage is considered, and it is argued that some of the factors responsible for the problems encountered in the modeling effort are of a nontechnical nature. >
198 citations
"A physical and scalable I-V model i..." refers background or methods in this paper
...A set of Benchmark tests [1], [2] have been performed, using the devices from several different manufacturers, to check the model’s general applicability and robustness (lack of discontinuities), accuracy, and performance in circuit simulation [18]....
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...The continuity, accuracy, scalablility, and simulation performance are basic requirements for a MOSFET model to meet the needs of analog and mixed analog/digital circuit designs [1], [2]....
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...As discussed in [1], [2], characteristic of the model is a very important measure to a model used in analog circuit design....
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TL;DR: In this article, the authors present an accurate analytical IGFET model for short-channel devices down to sub-half micron channel lengths, which is described by a single drain current equation, valid for both weak and strong inversion regions of device operation.
Abstract: We present an accurate analytical IGFET model (PCIM), for short-channel devices down to sub-half micron channel lengths. The model is described by a single drain current equation, valid for both weak and strong inversion regions of device operation. The model contains a new velocity-field (/spl upsi/-/spl epsi/) relation for carriers in the channel region. Combining this relation with the channel length modulation expression, obtained using engineering approximations to the two-dimensional fields near the drain end in saturation, results in an accurate drain conductance equation. The value for the carrier saturated velocity extracted from the I-V data for different CMOS technologies is 7-8/spl times/10/sup 6/ cm/s for electrons and 5-6/spl times/10/sup 6/ cm/s for holes, consistent with the reported values. The model not only predicts accurate output conductance, which is important for analog design, but also accurately simulates intrinsic gate capacitances for short channel devices. Since the model is inherently continuous, device conductances and capacitances are smooth and continuous at the transition points. This continuity results in enhanced convergence properties of the circuit simulator SPICE. Because the model is physically based, the temperature dependence of device characteristics in the temperature range 0-120/spl deg/C can easily be predicted simply by taking the temperature dependence of the threshold voltage, carrier mobility and velocity saturation parameters. >
95 citations