A quantitative verification framework of SysML activity diagrams under time constraints

TLDR: A novel verification framework based on PRISM probabilistic model checker that takes the SysML activity diagram as input and produces their equivalent timed probabilism automata that is/are expressed in PRISM language is proposed.

Abstract: Formal verification framework for probabilistic systems is proposed.SysML activity diagrams is used for system modeling.Automatic transformation of activity diagram into PRISM language.The soundness of the proposed framework is proved. Time-constrained and probabilistic verification approaches gain a great importance in system behavior validation including avionic, transport risk assessment, automotive systems and industrial process controllers. They enable the evaluation of system behavior according to the design requirements and ensure their correctness before any implementation. Due to the difficulty of analyzing, modeling and verifying these large scale systems, we introduce a novel verification framework based on PRISM probabilistic model checker that takes the SysML activity diagram as input and produce their equivalent timed probabilistic automata that is/are expressed in PRISM language. To check the functional correctness of the system under test, the properties are expressed in PCTL temporal logic. To prove the soundness of our mapping approach, we capture the underlying semantics of both the SysML activity diagrams and their generated PRISM code. We found that the timed probabilistic equivalence relation between both semantics preserve the satisfaction of the system requirements. We present digital camera as case study to illustrate the applicability of the proposed approach and to demonstrate its efficiency by analyzing a performability properties.

Figures

Fig. 7. The transformation soundness.

Fig. 4. Digital camera activity diagram design.

Fig. 8. The verification of PCTL properties on the digital camera.

Fig. 9. The abstract SysML activity diagram for Property 4.

Table 2 TAC terms of SysML activity diagram artifacts.

Fig. 5. Syntax of Timing A

Frequently asked questions

Q1. What is the process step for software development?

The process step for software development starts from specification level based on components interactions and identify the Unsafe Control Actions which are formalized into temporal logic. 

Q2. What are the main constraints used to control the routing of control token over edges?

Control nodes such as join, fork, merge, decision, initial and final are used to control the routing of control token over edges and specify the sequence of actions (concurrency, synchronization). 

Q3. What are the advantages of the proposed approach in the context of predicting the behavior of systems?

The practical advantages of the proposed approach in the context of predicting the behavior of systems, consists on providing key decision for errors minimization and product cost reducing via probabilistic model checking. 

Q4. What are the limitations of the proposed approach?

The limitations of the proposed approach relate to the problem of state explosion, the authors explain in their work how to reduce the number of state by removing just the negligible states that are not time-constrained. 

Q5. What is the meaning of a control token on an incoming control flow?

A control token on an incoming control flow enables the execution of an action and offers a control token on outgoing control flow when action completes its execution. 

Q6. What is the main concern of formal verification methods?

formal verification methods have become essential tools for developing safety–critical systems, where its behavioral correctness is a main concern. 

Q7. What are the main challenges of software development?

Constraints on software development in terms of functionality, performance, reliability and time to market are becoming more stringent. 

Q8. How many time units should be turned off after turning on the camera?

For the third property, the minimum reward or minimum expected time that the TurnOff action should be activated after turning on the camera is equal to 3.448 time units. 

Q9. What is the main reason why accelerated verification is so beneficial?

accelerate the verification and maintenance process atpreliminary design is extremely beneficial as compared to fixing them at the testing phase. 

Q10. What is the simplest way to verify a SysML activity diagram?

Soeanu, Debbabi, and Hassaine (2007) propose a probabilistic verification of SysML activity diagram where the execution time of actions are represented as constraints (i.e. A note artifact in SysML activity diagram). 

Q11. What criteria are used to compare the framework to the existing works?

As a summary, in Table 1 the authors compare their framework to the existing works by taking consideration five criteria: SysML language, time constraints, data workflow, formalization, soundness and automation.