A reduced complexity decoder architecture via layered decoding of LDPC codes
06 Dec 2004-pp 107-112
TL;DR: The previously devised irregular partitioned permutation LDPC codes have a construction that easily accommodates a layered decoding and it is shown that the decoding performance is improved by a factor of two in the number of iterations required.
Abstract: We apply layered belief propagation decoding to our previously devised irregular partitioned permutation LDPC codes These codes have a construction that easily accommodates a layered decoding and we show that the decoding performance is improved by a factor of two in the number of iterations required We show how our previous flexible decoding architecture can be adapted to facilitate layered decoding This results in a significant reduction in the number of memory bits and memory instances required, in the range of 45-50% The faster decoding speed means the decoder logic can also be reduced by nearly 50% to achieve the same throughput and error performance In total, the overall decoder architecture can be reduced by nearly 50%
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TL;DR: This article describes the LDPC code design philosophy and how the broad requirements of 5G NR channel coding led to the introduction of novel structural features in the code design, culminating in anLDPC code that satisfies all the demands of5G NR.
Abstract: Turbo codes, prevalent in most modern cellular devices, are set to be replaced by LDPC codes as the code for forward error correction. This transition was ushered in mainly because of the high throughput demands for 5G New Radio (NR). The new channel coding solution also needs to support incremental-redundancy hybrid ARQ, and a wide range of blocklengths and coding rates, with stringent performance guarantees and minimal description complexity. In this article, we first briefly review the requirements of the new channel code for 5G NR. We then describe the LDPC code design philosophy and how the broad requirements of 5G NR channel coding led to the introduction of novel structural features in the code design, culminating in an LDPC code that satisfies all the demands of 5G NR.
269 citations
Cites background from "A reduced complexity decoder archit..."
...Quasi and Full Row Orthogonality: In a typical hardware implementation of a quasi-cyclic LDPC decoder [9], there are Z processors, where Z corresponds to the maximum lift value....
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...[9] D....
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27 May 2007
TL;DR: A new multi-rate architecture for decoding block LDPC codes in IEEE 802.11n standard that utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm is presented.
Abstract: We present a new multi-rate architecture for decoding block LDPC codes in IEEE 802.11n standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. Techniques of data-forwarding and out-of-order processing are used to deal with the irregularity of the codes. The decoder has the following advantages when compared to recent state-of-the-art architectures: 55% savings in memory, reduction of routers by 50% and increase of throughput by 2times.
262 citations
Cites methods from "A reduced complexity decoder archit..."
...TDMP is later studied and applied for different LDPC codes using SP and its variations[4], [5]....
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...When compared to other TDMP architectures based on BCJR [3] and SP [5], the total memory savings is 55% since all the TDMP architectures have the same savings in Q memory....
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...Moreover, due to the efficient data-flow graph, this architecture requires only one cyclic shifter, while the work in [3], [5], [7], [9] used two cyclic shifters....
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...The resulting decoder architecture has significantly lower requirements of logic, interconnection and memory as compared with recent state-ofthe-art implementations [3], [5], [8], [9], [11], [15]....
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TL;DR: This paper describes and analyzes low-density parity-check code families that support variety of different rates while maintaining the same fundamental decoder architecture and proposes a design method that maintains good graphical properties and hence low error floors for all rates.
Abstract: This paper describes and analyzes low-density parity-check code families that support variety of different rates while maintaining the same fundamental decoder architecture. Such families facilitate the decoding hardware design and implementation for applications that require communication at different rates, for example to adapt to changing channel conditions. Combining rows of the lowest-rate parity-check matrix produces the parity-check matrices for higher rates. An important advantage of this approach is that all effective code rates have the same blocklength. This approach is compatible with well known techniques that allow low-complexity encoding and parallel decoding of these LDPC codes. This technique also allows the design of programmable analog LDPC decoders. The proposed design method maintains good graphical properties and hence low error floors for all rates.
252 citations
Additional excerpts
...Layered Belief Propagation (LBP), a decoding method that improves the convergence speed and allows a low complexity hardware architecture, was introduced in [17] and [18]....
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Patent•
01 May 2008TL;DR: In this paper, a method and system for decoding low density parity check (LDPC) codes is presented, which includes an R select unit, a Q message first-in first-out (FIFO) memory, and a cyclic shifter.
Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.
229 citations
24 Jun 2007
TL;DR: A new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard that utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm is presented.
Abstract: We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2times when compared to the recent state-of-the-art decoder architectures.
196 citations
Cites methods from "A reduced complexity decoder archit..."
...LDPC codes can be decoded by Gallager’s iterative twophase message passing algorithm (TPMP), which involves check-node update and variable-node update as a two phase schedule....
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References
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29 Jun 1997
TL;DR: It is proved that sequences of codes exist which, when optimally decoded, achieve information rates up to the Shannon limit, and experimental results for binary-symmetric channels and Gaussian channels demonstrate that practical performance substantially better than that of standard convolutional and concatenated codes can be achieved.
Abstract: We study two families of error-correcting codes defined in terms of very sparse matrices "MN" (MacKay-Neal (1995)) codes are recently invented, and "Gallager codes" were first investigated in 1962, but appear to have been largely forgotten, in spite of their excellent properties The decoding of both codes can be tackled with a practical sum-product algorithm We prove that these codes are "very good", in that sequences of codes exist which, when optimally decoded, achieve information rates up to the Shannon limit This result holds not only for the binary-symmetric channel but also for any channel with symmetric stationary ergodic noise We give experimental results for binary-symmetric channels and Gaussian channels demonstrating that practical performance substantially better than that of standard convolutional and concatenated codes can be achieved; indeed, the performance of Gallager codes is almost as close to the Shannon limit as that of turbo codes
3,842 citations
TL;DR: This work designs low-density parity-check codes that perform at rates extremely close to the Shannon capacity and proves a stability condition which implies an upper bound on the fraction of errors that a belief-propagation decoder can correct when applied to a code induced from a bipartite graph with a given degree distribution.
Abstract: We design low-density parity-check (LDPC) codes that perform at rates extremely close to the Shannon capacity. The codes are built from highly irregular bipartite graphs with carefully chosen degree patterns on both sides. Our theoretical analysis of the codes is based on the work of Richardson and Urbanke (see ibid., vol.47, no.2, p.599-618, 2000). Assuming that the underlying communication channel is symmetric, we prove that the probability densities at the message nodes of the graph possess a certain symmetry. Using this symmetry property we then show that, under the assumption of no cycles, the message densities always converge as the number of iterations tends to infinity. Furthermore, we prove a stability condition which implies an upper bound on the fraction of errors that a belief-propagation decoder can correct when applied to a code induced from a bipartite graph with a given degree distribution. Our codes are found by optimizing the degree structure of the underlying graphs. We develop several strategies to perform this optimization. We also present some simulation results for the codes found which show that the performance of the codes is very close to the asymptotic theoretical bounds.
3,520 citations
06 May 2001
TL;DR: A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes to enable rapid convergence in the decoding algorithm to be translated into low decoder switching activity.
Abstract: A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply.
595 citations
06 Jun 1999
TL;DR: It is proved by an ensemble performance argument that these codes are asymptotically good in the sense of the minimum distance criterion and the flexibility in selecting the parameters makes them suitable for small and large block length forward error correcting schemes.
Abstract: We build a class of pseudo-random error correcting codes, called generalized low density codes (GLD), from the intersection of two interleaved block codes. GLD code performance approaches the channel capacity limit and the GLD decoder is based on simple and fast SISO (soft input-soft output) decoders of smaller block codes. GLD codes are a special case of Tanner codes and a generalization of Gallager's LDPC codes. It is also proved by an ensemble performance argument that these codes are asymptotically good in the sense of the minimum distance criterion. The flexibility in selecting the parameters of GLD codes makes them suitable for small and large block length forward error correcting schemes.
220 citations
03 Nov 2002
TL;DR: A shuffled version of the belief propagation algorithm for the decoding of low-density parity-check (LDPC) codes is proposed, and it is shown that when the Tanner graph of the code is acyclic and connected, the proposed scheme is optimal in the sense of MAP decoding and converges faster than the standard BP algorithm.
Abstract: In this paper, we propose a shuffled version of the belief propagation (BP) algorithm for the decoding of low-density parity-check (LDPC) codes. We show that when the Tanner graph of the code is acyclic and connected, the proposed scheme is optimal in the sense of MAP decoding and converges faster (or at least no slower) than the standard BP algorithm. Interestingly, this new version keeps the computational advantages of the forward-backward implementations of BP decoding. Both serial and parallel implementations are considered. We show by simulation that the new schedule offers better performance/complexity trade-offs.
169 citations