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Journal ArticleDOI

A Regular Layout for Parallel Adders

01 Mar 1982-IEEE Transactions on Computers (IEEE)-Vol. 31, Iss: 3, pp 260-264
TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Abstract: With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.

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Citations
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Book
29 Sep 2011
TL;DR: The Fifth Edition of Computer Architecture focuses on this dramatic shift in the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices.
Abstract: The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change. Updated to cover the mobile computing revolutionEmphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")Includes three review appendices in the printed text. Additional reference appendices are available online.Includes updated Case Studies and completely new exercises.

984 citations

Journal ArticleDOI
TL;DR: The performance of CMOS is described and variability isn't likely to decrease, since smaller devices contain fewer atoms and consequently exhibit less self-averaging, but the situation may be improved by removing most of the doping.
Abstract: Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.

575 citations


Cites background from "A Regular Layout for Parallel Adder..."

  • ...The three basic architectures are the ripple carry adder with a passgate-based Manchester carry chain (static and dynamic) [29], logarithmic carry-select (static, dynamic, and passgate) [17], and carry-lookahead (Kogge–Stone radix 2 and radix 4 [30], Han–Carlson [31], and Brent–Kung [ 32 ])....

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Book
01 Jan 1987
TL;DR: In this paper, the authors propose a method to improve the quality of education for children in the developing world:1Basicblnephrojスセy(生理;免疫・病理 ;分子生物学.
Abstract: 1 Basic nephrology(生理;免疫・病理;分子生物学;検査・診断) 2 Clinical nephrology(糸球体障害;尿細管・間質障害;全身性疾患と腎障害;水電解質異常;腎不全)

571 citations

Book
02 Nov 2007
TL;DR: This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology.
Abstract: The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. · Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes · Views of FPGA programming beyond Verilog/VHDL · Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

531 citations

Book
11 Sep 2007
TL;DR: This book provides an up-to-date account of RNSs and arithmetic and covers the underlying mathematical concepts of R NSs; the conversion between conventional number systems and RNSS; the implementation of arithmetic operations; various related applications are introduced.
Abstract: This book provides an up-to-date account of RNSs and arithmetic. It covers the underlying mathematical concepts of RNSs; the conversion between conventional number systems and RNSs; the implementation of arithmetic operations; various related applications are also introduced. In addition, numerous detailed examples and analysis of different implementations are provided.

423 citations

References
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Book
01 Dec 1989
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Abstract: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high-performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and Web technologies, and high-performance computing.

11,671 citations

Book
01 Jan 1978

2,993 citations


"A Regular Layout for Parallel Adder..." refers background in this paper

  • ...Index Terms: Addition, area-time complexity, carry lookahead, circuit design, combinational logic, models of computation, parallel addition, parallel polynomial evaluation, prefix computation, VLSI....

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Journal ArticleDOI
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.
Abstract: The prefix problem is to compute all the products x t o x2 . . . . o xk for i ~ k .~ n, where o is an associative operation A recurstve construction IS used to obtain a product circuit for solving the prefix problem which has depth exactly [log:n] and size bounded by 4n An application yields fast, small Boolean ctrcmts to simulate fimte-state transducers. By simulating a sequentml adder, a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n Is obtained for n-bit binary addmon The size can be decreased significantly by permitting the depth to increase by an addmve constant

1,159 citations


"A Regular Layout for Parallel Adder..." refers methods in this paper

  • ...Although the same idea was used by Ladner and Fischer [8], their results are not directly applicable because they ignored fan-out restrictions and used the gate count rather than area as a complexity measure....

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  • ...Although the same idea was used by Ladner and Fischer [8], their results are not directly applicable because they ignored fan out restrictions and used the gate count rather than area as a complexity measure....

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Book
01 Jan 1979

996 citations


Additional excerpts

  • ...See, for example, [1], [4], [6], [7], [11], [13], and [14]....

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Book
01 Jan 1978

488 citations


Additional excerpts

  • ...See, for example, [1], [4], [6], [7], [11], [13], and [14]....

    [...]