A scalable processing-in-memory accelerator for parallel graph processing
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Cites background from "A scalable processing-in-memory acc..."
...[16] [17] [18] [19] [20] [21]) approaches whereby computation is moved closer to memory to overcome long memory latencies and utilize large bandwidths....
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Cites background or methods from "A scalable processing-in-memory acc..."
...While Tesseract [10] targets graphanalysis workloads via MIMD processing and inter-core com-...
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...While Tesseract [10] targets graphanalysis workloads via MIMD processing and inter-core communication, such workloads are not row-dense or compact, and Tesseract is not row-oriented and would incur row-locality problems similar to multicores....
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...While processing-in-memory (PIM) has been around for decades [3, 4, 5, 6, 7, 8, 9, 10, 11, 12], there are three problems....
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References
14,696 citations
"A scalable processing-in-memory acc..." refers methods in this paper
...Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems....
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5,629 citations
"A scalable processing-in-memory acc..." refers methods in this paper
...For this purpose, we use METIS [27] to perform 512-way multi-constraint partitioning to balance the number of vertices, outgoing edges, and incoming edges of each partition, as done in a recent previous work [51]....
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...This is confirmed by the observation that Tesseract with METIS spends 59% of execution time waiting for synchronization barriers....
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4,019 citations
"A scalable processing-in-memory acc..." refers methods in this paper
...We evaluate our architecture using an in-house cycle-accurate x86-64 simulator whose frontend is Pin [38]....
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3,840 citations
"A scalable processing-in-memory acc..." refers methods in this paper
...Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems....
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...It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model....
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