Proceedings ArticleDOI
A scalable processing-in-memory accelerator for parallel graph processing
Junwhan Ahn,Sungpack Hong,Sungjoo Yoo,Onur Mutlu,Kiyoung Choi +4 more
- Vol. 43, Iss: 3, pp 105-117
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TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.Abstract:
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.read more
Citations
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Improving and complementing virtual memory using hardware techniques
TL;DR: This thesis proposes a range of hardware mechanisms to improve TLB performance and security mechanisms complementary to those provided by virtual memory and proposes lowoverhead mechanisms achieve this.
Posted Content
GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent
Heesu Kim,Hanmin Park,Taehyun Kim,Kwanheum Cho,Eojin Lee,Soojung Ryu,Hyuk-Jae Lee,Kiyoung Choi,Jinho Lee +8 more
TL;DR: GradPIM as mentioned in this paper is a processing-in-memory architecture which accelerates parameter updates of deep neural networks training by extending DDR4 SDRAM to utilize bank-group parallelism.
Proceedings ArticleDOI
A High-Performance Processing-in-Memory Accelerator for Inline Data Deduplication
TL;DR: A highperformance processing-in-memory accelerator for inline data deduplication, called Deduplication Unit (DU) to reduce the latency and power consumption, and place the DUs in a base die or core dies of a 3D stacked memory to improve performance.
Proceedings ArticleDOI
CHOPPER: A Compiler Infrastructure for Programmable Bit-serial SIMD Processing Using Memory in DRAM
TL;DR: ChopPER as discussed by the authors is a new compiler infrastructure for bit-serial SIMD PUD architectures, which exploits bit-slicing compilers to enable automatic memory allocation and code generation, from naturally-expressive codes (i.e. similar to Parallel Haskell) into the "SIMD-Within-A-Register"-style codes, and introduces a new abstraction called virtual code emitter, to make Bit-serial PUD architecture exploit Memory-Level Parallelism more effectively.
Proceedings ArticleDOI
Dataflow based Near Data Computing Achieves Excellent Energy Efficiency
TL;DR: Dataflow processing in memory (DFPIM) is introduced which melds near data computing, dataflow architecture, coarse-grained reconfigurable logic, and 3D-DRAM technologies to provide high performance and very high energy efficiency for stream oriented and big data application kernels.
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