Proceedings ArticleDOI
A scalable processing-in-memory accelerator for parallel graph processing
Junwhan Ahn,Sungpack Hong,Sungjoo Yoo,Onur Mutlu,Kiyoung Choi +4 more
- Vol. 43, Iss: 3, pp 105-117
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TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.Abstract:
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.read more
Citations
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Proceedings ArticleDOI
TransPIM: A Memory-based Acceleration via Software-Hardware Co-Design for Transformer
TL;DR: TransPIM as discussed by the authors adopts a token-based dataflow to avoid the expensive inter-layer data movements introduced by previous layer-based Dataflow, and introduces lightweight modifications in the conventional high bandwidth memory architecture to support PIM-NMC hybrid processing and efficient data communication for accelerating Transformer-based models.
Proceedings ArticleDOI
NEMESYS: near-memory graph copy enhanced system-software
TL;DR: NEMESYS is an efficient implementation of the PGAS RPC, which outsources the memory-intensive and cache unfriendly graph copy operation to near-memory hardware accelerators and integrates these near- Memory Graph Copy Enhanced SYstem-Software into the system-software, opaque to the application programmer.
Journal ArticleDOI
An Architecture for Integrated Near-Data Processors
TL;DR: The inevitable start-up penalty regarding coherence and data writeback is quantified, and it is argued that near-data processing workloads should access data several times to offset this penalty.
Posted Content
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems.
Ronny Ronen,Adi Eliahu,Orian Leitersdorf,Natan Peled,Kunal Korgaonkar,Anupam Chattopadhyay,Ben Perach,Shahar Kvatinsky +7 more
TL;DR: Bitlet as discussed by the authors is an analytical modeling tool that can be used, in a parameterized fashion, to estimate the performance and the power/energy of a PIM-based system and thereby assess the affinity of workloads for PIM as opposed to traditional computing.
Proceedings ArticleDOI
Memory Coalescing for Hybrid Memory Cube
Xi Wang,John D. Leidel,Yong Chen +2 more
TL;DR: A novel memory coalescer methodology is introduced that facilitates memory bandwidth efficiency and the overall performance through an efficient and scalable memory request coalescing interface for HMC.
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