A scalable processing-in-memory accelerator for parallel graph processing
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Cites background from "A scalable processing-in-memory acc..."
...Tesseract [2] is a specialized NMP architecture for graph processing that employs graph-processing-specific prefetching schemes to utilize the ample available memory band-...
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...data movement makes NMP architectures an inherently better fit for in-memory data analytics than traditional CPU-centric architectures, triggering a recent NMP research wave [2, 3, 23, 24, 59, 60]....
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3 citations
Cites background from "A scalable processing-in-memory acc..."
...[43] have proposed the Tesseract architecture, where programmable graph accelerators are integrated into a 3D memory....
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3 citations
References
14,696 citations
"A scalable processing-in-memory acc..." refers methods in this paper
...Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems....
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13,327 citations
5,629 citations
"A scalable processing-in-memory acc..." refers methods in this paper
...For this purpose, we use METIS [27] to perform 512-way multi-constraint partitioning to balance the number of vertices, outgoing edges, and incoming edges of each partition, as done in a recent previous work [51]....
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...This is confirmed by the observation that Tesseract with METIS spends 59% of execution time waiting for synchronization barriers....
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4,019 citations
"A scalable processing-in-memory acc..." refers methods in this paper
...We evaluate our architecture using an in-house cycle-accurate x86-64 simulator whose frontend is Pin [38]....
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3,840 citations
"A scalable processing-in-memory acc..." refers methods in this paper
...Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems....
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...It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model....
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