Proceedings ArticleDOI
A scalable processing-in-memory accelerator for parallel graph processing
Junwhan Ahn,Sungpack Hong,Sungjoo Yoo,Onur Mutlu,Kiyoung Choi +4 more
- Vol. 43, Iss: 3, pp 105-117
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TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.Abstract:
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.read more
Citations
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Proceedings ArticleDOI
OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations
TL;DR: OrderLight as mentioned in this paper proposes a lightweight memory ordering primitive for PIM use cases, which moves away from core-centric ordering enforcement and considerably reduces the overheads of enforcing correctness, achieving a 5.5 to 8.5 × speedup over traditional fences.
Journal ArticleDOI
Multi-Node Acceleration for Large-Scale GCNs
TL;DR: The communication pattern and challenges of multi-node acceleration for GCNs on large-scale graphs are identified, and a topology-aware multicast mechanism with a one put per multicast message-passing model is proposed to reduce transmissions and alleviate network bandwidth requirements.
Journal ArticleDOI
Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks
TL;DR: CAMBRICON-G as discussed by the authors is a novel accelerator for efficient processing of both dynamic and static GNNs, which validates both the versatility and energy efficiency of CAMBRICon-G.
Journal ArticleDOI
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins
TL;DR: This dissertation rigorously characterizes many modern commodity DRAM devices and shows that by exploiting DRAM access timing margins within manufacturer-recommended DRAM timing specifications, this dissertation can significantly improve system performance, reduce power consumption, and improve device reliability and security.
Proceedings ArticleDOI
A Customized Processing-in-Memory Architecture for Biological Sequence Alignment
TL;DR: A processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications is proposed, composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture.
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