Book ChapterDOI
A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module
Rohan S. Adapur,S. Satheesh Kumar +1 more
- pp 62-68
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TLDR
This paper studies the operation and working of a Dual Dynamic node hybrid flip-flop (DDFF-ELM) with an embedded logic module that is one of the most efficient D-Flip-flops in terms of power and delay as compared to other dynamic flip flops.Abstract:
In this paper we study the operation and working of a Dual Dynamic node hybrid flip-flop (DDFF-ELM) with an embedded logic module. It is one of the most efficient D-Flip-flops in terms of power and delay as compared to other dynamic flip flops. A double exponential current pulse is passed to the sensitive nodes of the circuit to model a radiation particle strike in the circuit. The faulty output is then corrected using a radiation hardening by design technique. All the circuits are implemented using Cadence 90 nm technology and a comparison is made between the power and delay of already implemented D- flip-flops.read more
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Journal ArticleDOI
Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops
Ehab A. Hamed,Inhee Lee +1 more
TL;DR: Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop is used as a reference design for this comparison.
References
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Journal ArticleDOI
Modeling ionizing radiation effects in solid state materials and CMOS devices
TL;DR: An approach whereby defect distributions along the bottom and sidewall of the STI are calculated, incorporated into implicit surface potential equations, and ultimately used to model radiation-induced leakage currents in MOSFET structures and integrated circuits is described.
Proceedings ArticleDOI
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors
TL;DR: A new principle is proposed for designing low-cost highly robust storage cells and several transistor level implementations to cope with SEUs affecting latches and flip-flops.
Proceedings ArticleDOI
Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies
TL;DR: A novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs and the results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch.
Journal ArticleDOI
Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic
K. Absel,L. Manuel,R. K. Kavitha +2 more
TL;DR: The performance improvements indicate that the proposed designs are well suited for modern high-performance designs where power dissipation and latching overhead are of major concern.
Proceedings ArticleDOI
TSPC-DICE: A single phase clock high performance SEU hardened flip-flop
TL;DR: In this article, a single-phase clock (TSPC) flip-flop is proposed that is robust against radiation-induced single event upsets (SEUs) or soft errors.