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Journal ArticleDOI

A storage-based built-in test pattern generation method for scan circuits based on partitioning and reduction of a precomputed test set

01 Nov 2002-IEEE Transactions on Computers (IEEE Computer Society)-Vol. 51, Iss: 11, pp 1282-1293
TL;DR: The effectiveness of the proposed built-in test pattern generation method for scan circuits as a stand-alone procedure and as part of a scheme where random patterns are first applied to detect easy-to-detect faults is demonstrated.
Abstract: We describe a built-in test pattern generation method for scan circuits. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The sets are stored on-chip and the on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time. We describe two schemes for reducing the set sizes, one where each set stores the values of one subset of primary inputs or state variables and one where a single set is used to store values of different subsets of state variables. We demonstrate the effectiveness of the proposed method as a stand-alone procedure and as part of a scheme where random patterns are first applied to detect easy-to-detect faults. In the latter case, the proposed method is applied to detect the hard-to-detect faults that remain undetected.
Citations
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Journal ArticleDOI
Irith Pomeranz1
TL;DR: It is made the new observation that by keeping the same number of compressed tests and applying several different tests based on every compressed test, it is possible to improve the quality of the test set applied to the circuit.
Abstract: Test data compression is based on storage of compressed tests and use of on-chip decompression logic for test application. Further reductions in the input test data volume are achieved by methods that apply several different tests based on every compressed test. This article makes the new observation that by keeping the same number of compressed tests and applying several different tests based on every compressed test, it is possible to improve the quality of the test set applied to the circuit. This article studies such an approach for path delay faults (PDFs) using a linear-feedback shift register (LFSR) as the decompression logic. Because of the nature of PDFs, targeting an extended subset of PDFs increases the confidence that important PDFs are detected. However, the benefit of detecting additional faults may not justify an increase in the number of stored tests. The approach suggested in this article is used for detecting an extended subset of target PDFs using the same set of LFSR seeds. Extra clocking of the LFSR is used for obtaining scan-in states for several new two-cycle tests based on the same seed. Experimental results for benchmark circuits demonstrate the effectiveness of this approach.

7 citations


Cites methods from "A storage-based built-in test patte..."

  • ...This is also the basis for the approach described in [6]....

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Journal ArticleDOI
Irith Pomeranz1
TL;DR: This article explores a tradeoff between the amount of stored test data and the comprehensiveness of the test set that can be applied in a specific context that has the following main features: 1) the initial storedtest data is based on a stuck-at test set; 2) the target faults are single-cycle gate-exhaustive faults; and 3).
Abstract: Built-in self-test (BIST) approaches are suitable for in-field testing since they do not require a tester for storage and application of test data. They also reduce the security vulnerabilities associated with loading and unloading of external test data into scan chains. As technologies evolve, in-field testing needs to address more complex defect and aging mechanisms that require specific deterministic tests. This can be addressed by BIST approaches that store test data on-chip and use the data for on-chip generation of both random and deterministic tests. In this case, there is a tradeoff between the amount of stored test data and the comprehensiveness of the test set that can be applied. This article explores this tradeoff in a specific context that has the following main features: 1) the initial stored test data is based on a stuck-at test set; 2) the target faults are single-cycle gate-exhaustive faults; and 3) the stored test data is enhanced gradually by test data based on a gate-exhaustive test set to increase the coverage of gate-exhaustive faults.

6 citations

Proceedings ArticleDOI
Irith Pomeranz1
05 Apr 2020
TL;DR: Two methods that have not been used before for test data compression are considered in the context where a linear-feedback shift-register is used as part of the decompression logic, and tests are compressed into seeds for the LFSR.
Abstract: Test data compression methods reduce the input storage requirements of a test set by storing compressed tests. To enhance the ability to reduce the input test data volume, earlier approaches use the same input test data to apply several different tests. This paper considers two methods that have not been used before for this purpose. The methods are considered in the context where a linear-feedback shift-register (LFSR) is used as part of the decompression logic, and tests are compressed into seeds for the LFSR. The first method complements a bit of a seed to obtain a different test than the one produced by the uncomplemented seed. The second method uses the same seed for different LFSRs to produce different tests. The two methods are used together to demonstrate the advantages of a hybrid approach where the methods complement each other. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of a hybrid approach.

4 citations


Cites methods from "A storage-based built-in test patte..."

  • ...To enhance the ability to reduce the input test data volume, the approaches described in [4]-[11] use the same input test data to apply several tests....

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  • ...Each one of these methods can also be used alone or together with the methods described in [4]-[11]....

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  • ...In [4] and [8], the input test data is partitioned, and different combinations of the stored data are used for applying an increased number of tests....

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Journal ArticleDOI
Irith Pomeranz1
TL;DR: A new approach for applying several different tests based on every seed is introduced, which pads a seed in different ways to obtain new seeds for LFSRs with more bits, all of which can be implemented by a single programmable LFSR.
Abstract: In a commonly used test data compression method, the on-chip decompression logic is based on a linear-feedback shift-register ( $LFSR$ ), and compressed tests consist of seeds for the $LFSR$ . A seed can be modified and used for applying several different tests. This reduces the input test data volume further than the basic test data compression method. In this context, this article introduces a new approach for applying several different tests based on every seed. The new approach pads a seed in different ways to obtain new seeds for LFSR s with more bits, all of which can be implemented by a single programmable LFSR . The advantage of using LFSR s with more bits is that they are effective in detecting more target faults, thus supporting test compaction together with a reduction in the input test data volume. The experimental results for benchmark circuits demonstrate these points.

3 citations


Cites methods from "A storage-based built-in test patte..."

  • ...When the same compressed input test data are used for applying several different tests, the input test data volume is reduced further [4]–[12]....

    [...]

01 Jan 2012
TL;DR: This paper presents an equivalent approach to the design of code converters via the well-known k-map method, a generalization of a storage-based built-in test pattern generation method for reducing storage requirements and test application time in circuits.
Abstract: Data compression is important in the computing process because it helps to reduce the space occupied by a file, which normally leads to the reduction in the time taken to access the file. Files which may be compressed include text, images, video/speech and sound. Data compression algorithms have been developed and applied to several areas including neural networks, bioinformatics, database management systems, wireless systems, error detection and correction codes, fractals etc. Since computer/communication codes are binary texts, they may be compressed using binary text compression algorithms. By considering two binary texts which can be modeled as subsets of Unicode, namely the numerics of a 7-bit subset of the Information Processing Code (IPC) and the numerics of the 7-bit American Standard Code for Information Interchange (ASCII) respectively, this paper presents a comparative analysis of the compression properties of these two texts using a binary text compression algorithm. The algorithm is a generalization of a storage-based built-in test pattern generation method for reducing storage requirements and test application time in circuits. This algorithm is then applied to the design of an IPC to ASCII code converter. Code converters are circuits which accept input codes in one form and translate them to present equivalent values in a different format as the output code. They are useful in real-time control systems and data acquisition systems, such as aviation systems and patient-monitoring systems in hospitals, which require the use of different sensors to continuously monitor the computer. This paper thus presents an equivalent approach to the design of code converters via the well-known k-map method.

3 citations


Cites methods from "A storage-based built-in test patte..."

  • ...The binary text data compression algorithm used in the paper is a generalization of a storage-based built-in test pattern generation method described in [14] for reducing storage requirements and test application time in circuits....

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  • ...The algorithm, which is a generalization of a storage-based built-in test pattern generation method for reducing storage requirements and test application time in circuits [14], is then applied to the design of an IPC to ASCII code converter....

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References
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Proceedings ArticleDOI
21 Oct 1995
TL;DR: This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry and the different test sets and test conditions are described.
Abstract: This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for CrossCheck, Very-Low-Voltage, IDDQ and delay tests are also given.

286 citations


"A storage-based built-in test patte..." refers result in this paper

  • ...It was established in earlier works (e.g., [ 4 ] and [5]) that n-detection test sets for stuck-at faults (i.e., test sets that detect each stuck-at fault n times, where n> 1) are effective in detecting defects....

    [...]

  • ...We present experimental results to support this point by showing that the extra tests applied to the circuit are effective in detecting the circuit faults multiple times [ 4 ], [5]....

    [...]

Journal ArticleDOI
TL;DR: New cost-effective heuristics for the generation of minimal test sets that reduce the number of tests and allow tests generated earlier in the test generation process to be dropped are presented.
Abstract: This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M

228 citations


"A storage-based built-in test patte..." refers methods in this paper

  • ...For ISCAS-89 benchmark circuits, the combinational test set is the compacted test set generated by the procedure from [ 18 ]....

    [...]

Proceedings ArticleDOI
20 Oct 1996
TL;DR: The effectiveness of the AC tests shows that targeting additional faults produces better quality than relying on peripheral coverage of existing tests, and all tests detect unique failures, indicating the presence of additional unmodelled faults.
Abstract: This paper investigates the relative effectiveness of scan-based AC tests, IDDQ tests and functional tests for the detection of defective chips, particularly those exhibiting delay faults. Data are presented from an experiment in which a production ASIC was tested with a number of scan and functional tests, together with IDDQ. Results show that all tests detect unique failures, indicating the presence of additional unmodelled faults. The effectiveness of the AC tests shows that targeting additional faults produces better quality than relying on peripheral coverage of existing tests.

159 citations


"A storage-based built-in test patte..." refers background in this paper

  • ...The importance of applying input sequences Ti of length higher than one is that it contributes to at-speed testing of the circuit, which is important for detecting delay defects [ 6 ], [7]....

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  • ...Although it is possible to detect all the circuit faults using primary input sequences of length one, input sequences that contain more than one vector contribute to at-speed testing of the circuit, which is important for detecting delay defects [ 6 ], [7]....

    [...]

Proceedings ArticleDOI
03 Oct 2000
TL;DR: The proposed scheme relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter and outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.
Abstract: In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical approaches for test width compression and with pseudorandom pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.

121 citations


"A storage-based built-in test patte..." refers background in this paper

  • ...Methods that consider other types of circuits or different test application schemes and achieve complete fault coverage were described in [11], [12], [13], [ 14 ], [15], [16], [17]....

    [...]

Proceedings ArticleDOI
30 Oct 2001
TL;DR: A novel architecture for scan-based mixed mode BIST relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques.
Abstract: A novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.

106 citations


"A storage-based built-in test patte..." refers background in this paper

  • ...Methods that consider other types of circuits or different test application schemes and achieve complete fault coverage were described in [11], [12], [13], [14], [15], [ 16 ], [17]....

    [...]