A study on detailed placement for FPGAs
02 Mar 2015-pp 1-6
TL;DR: This work studies the effect of two different detailed placement methods, i) wirelength-driven, and ii) timing-driven on a legalized placement by proposing a suitable strategy specifically for FPGAs.
Abstract: Recent Field Programmable Gate Arrays (FPGA) have high logic capacity and it requires fast yet high quality placement method for mapping a technology mapped netlist of a given complex digital design onto the FPGA chip. Analytical placement for FPGAs show significant scalability for large design compared to traditional simulated annealing based placement methods. However, the high quality placement achieved during global placement with overlap of logic blocks need to be legalized and fine-tuned during detailed placement efficiently in order to take advantage of the scalability of the analytical placer without compromising the quality. In this work, we study the effect of two different detailed placement methods, i) wirelength-driven, and ii) timing-driven on a legalized placement by proposing a suitable strategy specifically for FPGAs. The experimental results show significant improvements of the legalized placement in terms of half-perimeter wirelength and critical path delay, emphasizing the need for better detailed placement methodologies.
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Dissertation•
01 Jan 2018
TL;DR: This work presents an EDA tool that was developed for placing heterogeneous FPGAs aiming routability, and is split into two flows, one that was implemented for the ISPD 2016 Placement Contest and one with the partitioning algorithm hMETIS in the FPGA placement flow stage.
Abstract: FPGAs are semiconductor devices that can be reprogrammed to reach different application requirements after manufacturing. The architecture of an FPGA can be homogeneous, containing only standard blocks of an FPGA, IOs and CLBs, or heterogeneous, being able to include also other types of blocks such as memory blocks and DSPs. One of the steps required in the design flow of an FPGA is placement, in which positions for the inner components of the FPGA are selected, and it is highly dependent upon its architecture, varying dramatically from one family of FPGA devices to another. In this work, we present an EDA tool that was developed for placing heterogeneous FPGAs aiming routability. It is split into two flows, one that was implemented for the ISPD 2016 Placement Contest (ISPD. . . , 2016), in which, the tool got the 4th place, and one with the partitioning algorithm hMETIS (KARYPIS et al., 1999) in the FPGA placement flow stage.
1 citations
Dissertation•
01 Aug 2015
TL;DR: This paper aims to demonstrate the efforts towards in-situ applicability of EMMARM, which aims to provide real-time information about the physical properties of E-modulus and its applications in the construction and maintenance of substations.
Abstract: University of Minnesota M.S.E.E. thesis. August 2015. Major: Electrical Engineering. Advisor: Kiarash Bazargan. 1 computer file (PDF); viii, 50 pages.
1 citations
Cites background from "A study on detailed placement for F..."
...There are three main analytical placement steps [24], namely...
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References
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01 Sep 1997
TL;DR: In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Abstract: We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today's industrial designs.
1,133 citations
"A study on detailed placement for F..." refers methods in this paper
...The pioneering work on FPGA placement is a simulated annealing based method namely VPR [6], which minimizes both HPWL and critical path delay....
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...Figure 4 (b) shows actual detailed routing where misalignments are converted into right angle turns or bends Legal Placement l)Partition chip area into windows 2)Estimate delay using VPR[6] �----------------� ,-______ 4-_______ , 1 1 / : Assume Block v 1 : at position u : L______ ....
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...A delay matrix matrixDelay(�X, �y) is pre-computed as the total delay of a route including wire delay and switch box delay if the distance between two CLBs CI and C2 are �x and �y as in VPR[6]....
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...We routed all the placement results, namely, the input legal placement, proposed wire length-driven and timing driven detailed placement using VPR [6] tm) tseng 5.43 7436 ex5p 3.91 6253 apex4 4.01 7431 dsip 4.15 18387 diffeq 4.20 6823 alu4 4.12 6207 des 11.10 31295 bigkey 3.95 21136 seq 4.18 9278 apex2 4.57 9617 s298 8.89 6818 elliptic 7.52 28537 spla 6.98 21989 pdc 9.83 33696 ex 10 10 6.89 28159 Geometric Mean 5.74 15228.76 Normalized 1...
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...Finally the detailed placement obtained is routed using VPR [6]....
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01 Feb 1999
TL;DR: This paper opened up an entirely new research area, setting the framework for numerous packing algorithms that have become a fundamental part of any FPGA CAD flow.
Abstract: In 1999, most commercial FPGAs, like the Altera Flex and Xilinx Virtex FPGAs already had cluster-based logic blocks. However, the modeling and evaluation of these sorts of architectures was still in its infancy. In the previous year, Betz had shown that cluster-based logic blocks led to improved density. The real advantage of clustered-based logic blocks, though, was speed, as this paper demonstrates. In doing so, this paper opened up an entirely new research area, setting the framework for numerous packing algorithms that have become a fundamental part of any FPGA CAD flow.
279 citations
TL;DR: FastPlace-a fast, iterative, flat placement algorithm for large-scale standard cell designs based on the quadratic placement approach that produces a global placement with even cell distribution in a very short time and a hybrid net model that is a combination of the traditional clique and star models.
Abstract: In this paper, we present FastPlace-a fast, iterative, flat placement algorithm for large-scale standard cell designs. FastPlace is based on the quadratic placement approach. The quadratic approach formulates the wirelength minimization problem as a convex quadratic program that can be solved efficiently by some analytical techniques. However it suffers from some drawbacks. First, the resulting placement has a lot of overlap among cells. Second, the resulting total wirelength may be long as the quadratic wirelength objective is only an indirect measure of the linear wirelength. Third, existing net models tend to create a lot of nonzero entries in the connectivity matrix that slows down the quadratic program solver. To handle the above problems we propose: 1) an efficient cell shifting technique to remove cell overlap from the quadratic program solution and also accelerate the convergence of the solver. This technique produces a global placement with even cell distribution in a very short time; 2) an iterative local refinement technique to reduce the wirelength according to the half-perimeter measure; and 3) a hybrid net model that is a combination of the traditional clique and star models. This net model greatly reduces the number of nonzero entries in the connectivity matrix and results in a significant speedup of the solver. Experimental results show that FastPlace is on average 13.4/spl times/,102/spl times/, and 19.9/spl times/ faster than state-of-the art academic placers Capo, Dragon, and Gordian-Domino, respectively, on a set of IBM benchmarks.
206 citations
03 Apr 2005
TL;DR: A generalized force-directed algorithm embedded in mPL2's multilevel framework is presented, which produces the shortest wirelength among all published placers with very competitive runtime on the IBM circuits used in [29].
Abstract: Automatic circuit placement has received renewed interest recently given the rapid increase of circuit complexity, increase of interconnect delay, and potential sub-optimality of existing placement algorithms [13]. In this paper we present a generalized force-directed algorithm embedded in mPL2's [12] multilevel framework. Our new algorithm, named mPL5, produces the shortest wirelength among all published placers with very competitive runtime on the IBM circuits used in [29]. The new contributions and enhancements are: (1) We develop a new analytical placement algorithm using a density constrained minimization formulation which can be viewed as a generalization of the force-directed method in [16]; (2) We analyze and identify the advantages of our new algorithm over the force-directed method; (3) We successfully incorporate the generalized force-directed algorithm into a multilevel framework which significantly improves wirelength and speed. Compared to Capo9.0, our algorithm mPL5 produces 8% shorter wirelength and is 2X faster. Compared to Dragon3.01, mPL5 has 3% shorter wirelength and is 12X faster. Compared to Fengshui5.0, it has 5% shorter wirelength and is 2X faster. Compared to the ultra-fast placement algorithm: FastPlace, mPL5 produces 8% shorter wirelength but is 6X slower. A fast mode of mPL5 (mPL5-fast) can produce 1% shorter wirelength than Fast-Place1.0 and is only 2X slower. Moreover, mPL5-fast has demonstrated better scalability than FastPlace1.0.
200 citations
"A study on detailed placement for F..." refers background in this paper
...There has been a few papers [13], [14], [15] on detailed placement for standard cell designs....
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09 Apr 2006
TL;DR: The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 and the XDP legalizer and detailed placer and the ASPDAC06 and consistently produces robust, high-quality solutions to difficult instances of mixed-size placement in fast and scalable run time.
Abstract: The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently produces robust, high-quality solutions to difficult instances of mixed-size placement in fast and scalable run time. Best-choice clustering (ISPD05) is used to construct a hierarchy of problem formulations. Generalized force-directed placement guides global placement at each level of the cluster hierarchy. During the declustering pass from coarsest to finest level, large movable objects are gradually fixed in positions without overlapping with one another. This progressive legalization of large objects during continuous optimization supports determination of a completely overlap-free configuration as close as possible to the continuous solution. Various discrete heuristics are applied to this legalized placement in order to improve the final wirelength.
199 citations
"A study on detailed placement for F..." refers background in this paper
...There has been a few papers [13], [14], [15] on detailed placement for standard cell designs....
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