Journal ArticleDOI
A Suggestion for a Fast Multiplier
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TLDR
A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.Abstract:
It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, ?sec, and quotients in 3 ?sec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer.read more
Citations
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Graph-Based Algorithms for Boolean Function Manipulation
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Journal ArticleDOI
Very high-speed computing systems
TL;DR: In this paper, the authors classified very high-speed computers as follows: 1) Single Instruction Stream-Single Data Stream (SISD) 2) SIMD 3) MIMD 4) MISD-MIMD.
Book ChapterDOI
Parallel algorithms for shared-memory machines
TL;DR: In this paper, the authors discuss parallel algorithms for shared-memory machines and discuss the theoretical foundations of parallel algorithms and parallel architectures, and present a theoretical analysis of the appropriate logical organization of a massively parallel computer.
Book
Digital arithmetic
Milo D. Ercegovac,Toms Lang +1 more
TL;DR: Digital Arithmetic, two of the field's leading experts, deliver a unified treatment of digital arithmetic, tying underlying theory to design practice in a technology-independent manner, to develop sound solutions, avoid known mistakes, and repeat successful design decisions.
Journal ArticleDOI
Memory systems
TL;DR: Cache memories are a general solution to improving the performance of a memory system by placing smaller faster memories in front of larger, slower, and cheaper memories to approach that of a perfect memory system—at a reasonable cost.
References
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Journal ArticleDOI
A parallel arithmetic unit using a saturated-transistor fast-carry circuit
TL;DR: In this paper, a transistor switch technique for parallel addition is described, which is of particular importance in applications where a large number of switches have to be connected in series and where the propagation time of information through these switches has to be a minimum.