Proceedings ArticleDOI
A super-pixel based on-chip image compression for high speed CMOS image sensors
Deepak Mishra,Amandeep Kaur,Mukul Sarkar +2 more
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TLDR
A super-pixel based on-chip compression is proposed in this paper, which results in 49% of power saving and higher values of PSNR are observed as compared to the state-of-the-art on- chip compression techniques.Abstract:
A super-pixel based on-chip compression is proposed in this paper. The compression is achieved by reading only one sample for each super-pixel. The proposed technique and the corresponding circuit are simulated in MATLAB and UMC 180 nm CMOS technology, respectively. Higher values of PSNR are observed as compared to the state-of-the-art on-chip compression techniques. For the compression factor of 2, the implemented design results in 49% of power saving.read more
Citations
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Journal ArticleDOI
Content Driven On-Chip Compression and Time Efficient Reconstruction for Image Sensor Applications
TL;DR: The experiment shows that the compression of 86.2% can be achieved using the threshold of two intensity levels and the compressed image can be reconstructed with the PSNR of 45.87 dB.
Journal ArticleDOI
On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients
TL;DR: The proposed compressive acquisition technique for on-array image compression is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.
Journal ArticleDOI
A Power Efficient Image Sensor Readout With On-Chip $\delta$ -Interpolation Using Reconfigurable ADC
TL;DR: A low-power readout using reconfigurable cyclic ADC for CMOS image sensors is proposed, which reduces the total number of pixels to be read by taking advantage of pixel correlation, resulting in power saving and improvement in FoM.
Proceedings ArticleDOI
An On-Chip Interpolation Based Readout Scheme for Low-Power, High-Speed CMOS Image Sensors
TL;DR: A low-power, high-speed on-chip compression and reconstruction technique that takes the advantage of correlation between the consecutive pixels and reduces the total number of pixels to be read, which results in power saving.
Proceedings ArticleDOI
CMOS image sensor with adaptive readout scheme for low power applications
TL;DR: In this article, an adaptive readout scheme for low-power CMOS image sensors is proposed, where the entire pixel array is partitioned into square blocks, and the intensity range of each block is divided into a fix number of bins which are adapted to the intensity ranges of the block.
References
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Journal ArticleDOI
SLIC Superpixels Compared to State-of-the-Art Superpixel Methods
TL;DR: A new superpixel algorithm is introduced, simple linear iterative clustering (SLIC), which adapts a k-means clustering approach to efficiently generate superpixels and is faster and more memory efficient, improves segmentation performance, and is straightforward to extend to supervoxel generation.
Journal ArticleDOI
CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable Compressed Sensing
Y. Oike,A. El Gamal +1 more
TL;DR: A CMOS image sensor architecture with built-in single-shot compressed sensing with modest quality loss relative to normal capture and significantly higher image quality than downsampling is described.
Proceedings ArticleDOI
A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits
TL;DR: This paper presents a high-speed CMOS image sensor with on-chip parallel image compression circuits that consists of a pixel array, an A/D converter array with noise canceling function and an image compression processing element array and buffer memories.
Proceedings ArticleDOI
CMOS imager with focal-plane image compression based on the EZW algorithm
TL;DR: The design of a focal-plane image compression circuit for CMOS cameras achieves compression ratio around 3:1 through an iterative process which progressively reduces image resolution.