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Journal ArticleDOI

A survey of power estimation techniques in VLSI circuits

01 Dec 1994-IEEE Transactions on Very Large Scale Integration Systems (IEEE Educational Activities Department)-Vol. 2, Iss: 4, pp 446-455
TL;DR: A review of the power estimation techniques that have recently been proposed for very large scale integrated (VLSI) circuits is presented.
Abstract: With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed. >
Citations
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Proceedings ArticleDOI
Boris Köpf1, David Basin1
28 Oct 2007
TL;DR: A model of adaptive side-channel attacks which is combined with information-theoretic metrics to quantify the information revealed to an attacker is presented, which allows an attacker's remaining uncertainty about a secret as a function of the number of side- channel measurements made.
Abstract: We present a model of adaptive side-channel attacks which we combine with information-theoretic metrics to quantify the information revealed to an attacker. This allows us to express an attacker's remaining uncertainty about a secret as a function of the number of side-channel measurements made. We present algorithms and approximation techniques for computing this measure. We also give examples of how they can be used to analyze the resistance of hardware implementations of cryptographic functions to both timing and power attacks.

404 citations

Journal ArticleDOI
TL;DR: This work presents a new predictive system shutdown method to exploit sleep mode operations for power saving, using an exponential-average approach to predict the upcoming idle period and introduces two mechanisms, prediction-miss correction and pre-wakeup, to improve the hit ratio and to reduce the delay overhead.
Abstract: This paper presents a system-level power management technique for energy savings of event-driven application We present a new predictive system-shutdown method to exploit sleep mode operations for energy saving We use an exponential-average approach to predict the upcoming idle period We introduce two mechanisms, prediction-miss correction and prewake-up, to improve the hit ratio and to reduce the delay overhead Experiments on four different event-driven applications show that our proposed method achieves high hit ratios in a wide range of delay overheads, which results in a high degree of energy with low delay penaties

356 citations


Additional excerpts

  • ...Weintroducetwomechanisms,prediction­misscorrectionandpre-wakeup,toimprovethehitratio andtoreducethedelayoverhead....

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DissertationDOI
01 Jan 1997
TL;DR: It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design.
Abstract: The addition of two binary numbers is the fundamental and most often used arithmetic operation on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Therefore, bi¬ nary adders are crucial building blocks in very large-scale integrated (VLSI) circuits. Their efficient implementation is not trivial because a costly carrypropagation operation involving all operand bits has to be performed. Many different circuit architectures for binary addition have been proposed over the last decades, covering a wide range of performance characteristics. Also, their realization at the transistor level for full-custom circuit implemen¬ tations has been addressed intensively. However, the suitability of adder archi¬ tectures for cell-based design and hardware synthesis both prerequisites for the ever increasing productivity in ASIC design — was hardly investigated. Based on the various speed-up schemes for binary addition, a compre¬ hensive overview and a qualitative evaluation of the different existing adder architectures are given in this thesis. In addition, a new multilevel carryincrement adder architecture is proposed. It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design. These three adder architectures, which together cover the entire range of possible area vs. delay trade-offs, are comprised in the more general prefix adder architecture reported in the literature. It is shown that this universal and flexible prefix adder structure also allows the realization of various customized adders and of adders fulfilling arbitrary timing and area constraints. A non-heuristic algorithm for the synthesis and optimization of prefix adders is proposed. It allows the runtime-efficient generation of area-optimal adders for given timing constraints.

268 citations

Proceedings ArticleDOI
01 Jan 1995
TL;DR: This work surveys state-of-the-art optimization methods that target low power dissipation in VLSI circuits and considers the circuit, logic, architectural and system levels.
Abstract: We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

257 citations

Journal ArticleDOI
TL;DR: This paper surveys representative contributions to power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow that have appeared in the recent literature.
Abstract: Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital very-large-scale-integration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand high-speed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of high-end products to keep power under control, due to the increased costs of packaging and cooling this type of device. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of low-power VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature.

232 citations


Cites background from "A survey of power estimation techni..."

  • ...On the other hand, we do not discuss traditional logic-level (and below) techniques, since this subject is out of the scope of this paper (the interested reader may refer to [ 1 ]‐[4] for excellent surveys on this topic)....

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References
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Journal ArticleDOI
TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
Abstract: In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. We present experimental results from applying these algorithms to problems in logic design verification that demonstrate the practicality of our approach.

9,021 citations

Book
06 Dec 1982

6,033 citations

Journal ArticleDOI
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Abstract: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

2,690 citations

Journal Article
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Abstract: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations This optimum is achieved by trading increased silicon area for reduced power consumption >

2,337 citations


"A survey of power estimation techni..." refers background in this paper

  • ...The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]....

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