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Journal ArticleDOI

A Survey on FFT/IFFT Processors for Next Generation Telecommunication Systems

01 Mar 2018-Journal of Circuits, Systems, and Computers (World Scientific Publishing Company)-Vol. 27, Iss: 03, pp 1830001
TL;DR: A comparative study of efficient algorithms and architectures for FFT chip design is presented and it is recommended that mixed-radix/higher-radIX algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIM o and multi-user MIMo-based applications.
Abstract: The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most significant digital signal processing (DSP) techniques used in Orthogonal Frequency Division Multiplexing (OFDM)-based applications which include day-to-day wired/wireless communications, broadband access, and information sharing. The advancements in telecommunication technologies require an efficient FFT/IFFT processing device to meet the necessary specifications which depend on the particular application. A real-time implementation of high-speed FFT/IFFT processor with less area that operates in minimal power consumption is essential in designing an OFDM integrated chip. A comparative study of efficient algorithms and architectures for FFT chip design is presented in this paper. It is also recommended that mixed-radix/higher-radix algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIMO and multi-user MIMO-based applications.
Citations
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Journal ArticleDOI
TL;DR: It is shown that the effect of nonlinearity is shown to be negligible on MIMO-CE-OFDM signal, which is a promising technique for high-performance 5G broadband wireless communications.
Abstract: Orthogonal frequency division multiplexing (OFDM) is a multicarrier transmission system that can achieve high data rate over wireless channels At the same time, multiple input multiple output OFDM

20 citations

Proceedings ArticleDOI
19 Mar 2019
TL;DR: In this paper, the performance of ZF and MMSE detectors was evaluated with $(Nt\times Nr)$, (50 × 100) and ( 50 × 300) respectively antennas array, for various modulations techniques 16-QAM, 64 QAM, and 128 QAM.
Abstract: A Least Squares Channel Estimation (LSCE) method is designated for a Massive MIMO system combined with Orthogonal Frequency Division Multiplexing (OFDM) and higher order modulation technique. The performance of ZF and MMSE detectors is evaluated with $(Nt\times Nr)$ , (50 × 100) and (50 × 300) respectively antennas array, for various modulations techniques 16-QAM, 64-QAM, and 128-QAM, and for various OFDM sub-carriers 64, 256, 512 and 1024. The performance is determined in terms of Bit Error Rate (BER). Increasing the number of Bits/symbol provides an increase of BER both the ZF and MMSE detectors for an antennas array 50 × 100; Whereas increasing the number of OFDM sub-carriers provides a decreasing of BER. Combining 128-QAM modulation with 1024-sub-carriers and increase the receiver antennas array three times (i.e., 50 × 300), decreases more the BER both the ZF and MMSE detectors. Consequently the ZF and MMSE detectors provide a best BER so a best system performance.

15 citations


Cites background or methods from "A Survey on FFT/IFFT Processors for..."

  • ...The direct implementation of DFT demand K(2) and K(K − 1) complex multiplications and additions respectively [6]....

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  • ...For this purpose, frequency division multiplexing packet digital data, which will be called OFDM symbol and module each data by a different carrier at the same time [6]....

    [...]

Journal ArticleDOI
TL;DR: In this paper, complex multipliers in the FFT processors are replaced by area and power efficient approximate multipliers, and experimental results show that the proposed 16-point FFT architecture incorporating approximate complex multiplier achieves an area and power efficiency of 33.47% and 1.8% respectively.
Abstract: Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) computations involve quite a large number of complex multiplications and complex additions. Optimizing the FFT processing elements in terms of complex multiplication reduces area and power consumption. In this paper, complex multipliers in the FFT processors are replaced by area and power efficient approximate multipliers. Approximate arithmetic computation appears to be effective solution for the systems that exhibit an intrinsic error tolerance. The computational errors arising because of approximation can be considered as trade-off for the significant gains in power and area. Approximate 8- and 16-bit multipliers are used in radix-2 butterfly unit which is the crucial computational component in FFT/IFFT processing. The designed FFT/IFFT processing units are analyzed, synthesized and simulated in Altera Cyclone II EP2C35F672C6 Field Programmable Gate Array (FPGA) device. Experimental results show that the proposed 16-point FFT architecture incorporating approximate complex multiplier achieves an area and power efficiency of 33.47% and 1.8% respectively compared to accurate 16-point FFT processor. The 8-point and 16-point Decimation In Time (DIT)—FFT incorporating approximate computational elements operate at a speed of 26.69 Gbps and 46.20 Gbps, respectively.

14 citations

Journal ArticleDOI
TL;DR: A least squares channel estimation in the UpLink transmission for a Massive MIMO systems in 5G wireless communications, combined with Orthogonal Frequency Division Multiplexing and higher-order M-QAM modulation results in faster data rates and higher spectral efficiency levels for the communication systems.
Abstract: This paper presents a least squares channel estimation (LSCE) in the UpLink transmission for a Massive MIMO systems in 5G wireless communications, combined with Orthogonal Frequency Division Multiplexing and higher-order M-QAM modulation. The Mean Square Error (MSE) of the LSCE is computed, and the performance of ZF, MMSE and V-BLAST detectors is also evaluated. Using 128-QAM modulation (i.e., increasing the noise system sensibility) with 1024 subcarriers and increasing the Base Station antennas array decreases more the Bit Error Rate (BER) for the ZF, MMSE and V-BLAST detectors with respect to the MSE. The performance degradation both ZF and MMSE compared to V-BLAST is negligible in a high receive antennas; hence, faster data rates and higher spectral efficiency levels for the communication systems. Consequently, the ZF, MMSE and V-BLAST detectors achieve a better BER with respect to channel estimation.

12 citations

Journal ArticleDOI
TL;DR: This research article presents an implementation of high-performance Fast Fourier Transform (FFT) and Inverse Fast Fouriers Transform (IFFT) core for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM)-based applications.
Abstract: This research article presents an implementation of high-performance Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) core for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM)-based applications. The radix-2 butterflies are implemented using arithmetic optimization technique which reduces the number of complex multipliers involved. High-performance approximate multipliers with negligible error rate are used to eliminate the power-consuming complex multipliers in the radix-2 butterflies. The FFT/IFFT prototype using the proposed high-performance butterflies are implemented using Altera Quartus EP2C35F672C6 Field Programmable Gate Array (FPGA) which yields 40% of improved logic utilization, 33% of improved timing parameters, and 14% of improved throughput rate. The proposed optimized radix-2-based FFT/IFFT core was also implemented in 45-nm CMOS technology library, using Cadence tools, which occupies an area of 143.135 mm2 and consumes a power of 9.10 mW with a maximum throughput of 48.44 Gbps. Similarly, the high-performance approximate complex multiplier-based optimized FFT/IFFT core occupies an area of 64.811 mm2 and consumes a power of 6.18 mW with a maximum throughput of 76.44 Gbps.

9 citations

References
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Book
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9,038 citations

MonographDOI
01 Jan 2005

5,919 citations

Journal ArticleDOI
TL;DR: Orthogonal frequency division multiplexing for MIMO channels (MIMO-OFDM) is considered for wideband transmission to mitigate intersymbol interference and enhance system capacity.
Abstract: Multiple transmit and receive antennas can be used to form multiple-input multiple-output (MIMO) channels to increase the capacity by a factor of the minimum number of transmit and receive antennas. In this paper, orthogonal frequency division multiplexing (OFDM) for MIMO channels (MIMO-OFDM) is considered for wideband transmission to mitigate intersymbol interference and enhance system capacity. The MIMO-OFDM system uses two independent space-time codes for two sets of two transmit antennas. At the receiver, the independent space-time codes are decoded using prewhitening, followed by minimum-Euclidean-distance decoding based on successive interference cancellation. Computer simulation shows that for four-input and four-output systems transmitting data at 4 Mb/s over a 1.25 MHz channel, the required signal-to-noise ratios (SNRs) for 10% and 1% word error rates (WER) are 10.5 dB and 13.8 dB, respectively, when each codeword contains 500 information bits and the channel's Doppler frequency is 40 Hz (corresponding normalized frequency: 0.9%). Increasing the number of the receive antennas improves the system performance. When the number or receive antennas is increased from four to eight, the required SNRs for 10% and 1% WER are reduced to 4 dB and 6 dB, respectively. Therefore, MIMO-OFDM is a promising technique for highly spectrally efficient wideband transmission.

546 citations

Proceedings ArticleDOI
15 Apr 1996
TL;DR: A new VLSI architecture for a real-time pipeline FFT processor is proposed, derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach, which has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the Radix-2 algorithm.
Abstract: A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-2/sup 2/ algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-2/sup 2/ algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log/sub 4/N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL.

410 citations

Journal ArticleDOI
TL;DR: This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.
Abstract: This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.

319 citations