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A system-level multiprocessor system-on-chip modeling framework
Virk, Kashif Munir; Madsen, Jan
Published in:
International Symposium on System-on-Chip, 2004. Proceedings.
Link to article, DOI:
10.1109/ISSOC.2004.1411154
Publication date:
2004
Document Version
Publisher's PDF, also known as Version of record
Link back to DTU Orbit
Citation (APA):
Virk, K. M., & Madsen, J. (2004). A system-level multiprocessor system-on-chip modeling framework. In
International Symposium on System-on-Chip, 2004. Proceedings. IEEE.
https://doi.org/10.1109/ISSOC.2004.1411154
A
System-level Multiprocessor System-on-Chip Modeling Framework
Kashif Virk Jan Madsen
Informatics and Mathematical Modeling
Technical University of Denmark
{virkjan} @imm.dtu.dk
Abstract
We present a system-level modeling framework
to
model system-on-chips
(SoC)
consisting of hetemgeneous
muliprocessors and network-on-chip communication sfmc-
tures in order
to
enable the developers of todays
SoC
de-
signs
to
take advantage
of
the flexibility
and
scalability
of
network-on-chip and rapidly explore
high-level
design al-
tematives
to
meet their system requirements. We present a
modeling appmach for developing high-level performance
models
for
these
SoC
designs and outline how this system-
level performance analysis capability can be integrated into
an overall environment for eficient
SoC
design.
We
show
how
a
hand-held multimedia terminal, consisting
of
JPEG,
MP3
and
GSM applications, can be modeled as a multipm-
cessor
SoC
in
our
framework.
1
Introduction
Networks on chip (NoC's) are receiving considerable at-
tention
as
a
solution to
the
interconnect problem in highly-
complex chips.
The
reason is two-fold. First, NoC's help
resolve the electrical problems in new deep-submicron tech-
nologies,
as
they structure and manage global wires. At the
same time, they share wires, lowering their number and in-
creasing their utilization.
NoC's
can
also
be energy-efficient
and reliable, and are scalable compared to buses. Sec-
ond, NoC's
also
decouple computation from communica-
tion, which is essential in managing the design of billion-
transistor chips. NoC's achieve
this
decoupling because
they are traditionally designed using protocol stacks, which
provide well-defined interfaces separating communication
service usage from service implemenration. Using net-
works for on-chip communication when designing systems-
on-chip (SoC), however, raises
a
number of new issues that
must be taken into account.
This
is
because, in contrast
to existing on-chip interconnects (e.g., buses, switches,
or
point-to-point wires), where the communicating modules
are directly connected, in
a
NoC, the modules communicate
remotely
via
network nodes.
As
a
result, interconnect arbi-
tration changes from centralized to distributed, and issues
like out-of order transactions, higher latencies, and end-to-
end flow control must be handled either by the intellectual
property block
(IP)
or
by the network.
Multimedia
is
an increasingly important application area
for
NoC platforms, in particular, for
the
new generations
of
hand-held devices where high-quality audio and video
have to he delivered under strict resource and energy con-
straints. Baicaanu et
al.
[
I]
have analyzed the consequences
of applying rate-monotonic
(RM)
scheduling on multime-
dia applications, i.e. an
MPEG
player. They argue that the
complexity and dynamic behavior of this type of application
makes static solutions infeasible and, hence, adaptive meth-
ods have to be used.
[7]
presents a more extensive survey
of
OS
support, and, in particular, scheduling methods for
multimedia applications. The presented methods are dis-
cussed in the context of basic system requirements for mul-
timedia. In
[5],
Nieb and Lam present an integrated pro-
cessor scheduling algorithm for multimedia applications,
where both audio and video streams have to be manipulated
within well-defined timing requirements, whereas conven-
tional interactive and batch activities still have to be han-
dled. The scheduling algorithm uses two different schedul-
ing policies within
the
same scheduler, i.e. multimedia tasks
are handled by an
EDF
scheduling algorithm, whereas con-
ventional tasks
are
scheduled by
a
Round-Robin scheduling
algorithm. The approach of having several scheduling poli-
cies within the same scheduler is further explored by Goyal
et al. in
[3].
They present a framework for hierarchical CPU
scheduling in which different scheduling algorithms are em-
ployed for different parts of
a
multimedia application in
or-
der to better support the variety of best-effort, bard, and soft
real-time characteristics which
are
typically found in mul-
timedia computing environments.
In
[6],
the scheduling of
audio and video multimedia applications is brought to mul-
tiprocessor systems. Although
a
multiprocessor scheduling
algorithm has been presented, the network communication
latencies have not been taken into account.
In
this paper, we present
a
system-level NoC model,
which is an extension of
our
previous multiprocessor
SoC
modeling framework
[4].
The extended model is able to
model heterogeneous multiprocessor architectures intercon-
nected through
a
an on-chip network architecture, such
as
a
mesh
or
a
torus. We show how
a
hand-held multimedia
terminal, consisting of integrated
JPEG
encoding and de-
coding, and
Mp3
decoding
as
well
as
GSM
encoding and
decoding for the wireless transmission, can be modeled at
0-7803-8558-6/04/$20.00
02004
IEEE
81
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the system-level in
our
modeling framework.
2
System-Level Modeling
To address the system-level design challenges described
above, we need an extended system-on-chip design process,
including the effects of the network-on-chip, with the abil-
ity to evaluate options and make critical architectural deci-
sions based on
a
system-level representation in advance
of
a detailed design.
A
key pre-requisite is
a
library
of
ah-
stract component models that captures their respective per-
formance, power, and physical characteristics.
The
primary
goal
of system-level modeling for emhed-
ded systems is to formulate
a
model within which a broad
class of designs can be developed and explored. Moreover,
the difficulty of verifying the design of complex systems
can be reduced by decomposing
a
system into smaller sub-
systems, independently verifying an implementation of the
subsystems, and then proving that
the
composition of the
subsystem specifications satisfies the overall system speci-
fication.
In
order to do
so,
accurate modelling of the sys-
.em and
all
the interrelationships among the diverse proces-
sors,
software processes, physical interfaces and intercon-
nections is needed.
The
scheduling problem, central to the analysis of the
complexity of concurrent programs, depends on the way in
which the scheduled tasks are mapped on the processing
elements which, in tum, is linked with the physical archi-
tecture
of
the
computing platforms.
A
real-time operating system
is
meant to provide some
assurances ahout the timely performance
of
tasks. Unfortu-
nately, most mechanisms used in the basic RTOS services
are not compositional in nature. Even if a mechanism can
provide assurances individually to each task, there is no sys-
tematic way to provide assurances for an aggregate of two
except in trivial cases.
To
supporl
the designers of single chip-based embedded
systems, which includes multiprocessor platforms running
dedicated RTOS’s, we have developed a modeling environ-
ment based on SystemC
[2,4].
In
our
abstract RTOS model-
ing framework, we deal with generalized abstract tasks,
pro-
cessing elements, and communication infrastructures.
For
the purposes of modelling, three distinct but closely-related
RTOS services have heen identified, namely, task schedul-
ing, execution synchronization, and resource allocation.
3
Model Implementation
We
have implemented
our
system-level modeling frame-
work in SystemC. SystemC is in
a
class of languages that
target modeling of hardware and software systems, and it
has the desirable feature of being able to simulate models
at
a
very high level of abstraction together with low-level
ones. Figure
1
gives an overview of
our
system-level SoC
model, including the processor model and
the
NoC model
which will be described in
this
section.
CI
Figure
1.
System-level
System-on-Chip
model
3.1
Abstract
RTOS
Model
Our
abstract RTOS System Model
[2]
deals with the
analysis of the execution behavior
of
a
real-time applica-
tion running on a heterogeneous multiprocessor platform.
In
our
model, such an application is represented
as
a multi-
threaded application comprising
a
set of tasks where each
task,
z,
can be decomposed into
a
sequence of task seg-
ments,
zj.
Each task segment,
zj,
is required to precede
a
given set of other task segments. Moreover, each task seg-
ment also excludes
a
given set of other task segments for
the
use
of shared resources.
For
each task, we are given
a
release
time,
rk,
a release-time offset,
oi.
a
start
time,
sk,
a best-case execution time,
bcer,,
a
worst-case execution
time,
wcerj,
a
deadline,
d,,
a
period,
E,
and
a
context switch
time,
cswj.
A
similar set of parameters can
be
computed
for
each task segment,
z;,
relative to the beginning of the task
containing that task segment.
The
mu1tiprocesr:or platform
is
modelled
as
a
collection of Processing Elements,
PEk,
and Devices,
Dk,
interconnected by a set of Communica-
tion Channels,
Ck.
Each
PEk
is modelled in terms of the
RTOS services provided to the
tasks
comprising the appli-
cation. Based
on
the principle of composition, three basic
RTOS services are modeled
a
scheduler,
a
synchronizer,
and
a
resource allocator.
The
scheduler
is
modeled around the priority-based
pre-
emptive scheduling policy which is one of the most
pre-
ferred scheduling policies for the execution of tmks in real-
time systems due to its higher schedulability. According to
our
scheduler model, whenever
a
task becomes ready
or
fin-
ishes execution,
the
scheduler is called and it then
looks
for
a
ready task with maximal priority to continue execution.
In
our
synchronizer model, synchronization is regarded
as
82
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a
means to prevent undesirable task interleavings by the
scheduler.
Our
synchronizer model is responsible for
es-
tablishing the correctness of the results computed by the
multiprocessor platform and it implements the Direct Syn-
chronization
(DS)
protocol
[9].
3.2
Extension
of
the Abstract
RTOS
Model
to
Model
NoCs
For the
purpose
of forming
a
system-level NoC simula-
tion model, unlike
a
network simulator, we have abstracted
away all the low-level network details except
the
most es-
sential ones (e.g., topology, latency, etc.). We treat the on-
chip communication network
as a
communicationpmcessor
to reflect the servicing demands.
A
communication event
within this network is modeled
as
a
message
tusk,
T,,
ex-
ecuting on the communication processor. When one PE
wants to communicate with another PE,
a
2,
is fired on
the communication
processor.
Each
T,
represents commu-
nication only between two fixed set
of
predetermined PE’s.
Since a NoC
supports
concurrent communication,
T,’S
need
to be synchronized, allocated resources and scheduled
at-
cordingly. This is
a
property of the underlying NoC imple-
mentation, where the NoC allocator reflects
the
topology
and the NoC scheduler reflects the protocol.
A
resource
database, which is unique to each NoC implementation,
contains information on
all
its resources.
In
a
segmented
network, these resources are laid-out
as
two-dimensional
in-
terconnects and
are
acollection ofnodes (routers) and links.
The NoC allocation and scheduling algorithms map
a
T~
onto the available network resources.
NoC
Allocator:
The allocator translates
the
path re-
quirements of
a
T~
in terms of its resource require-
ments such
as
bandwidth, buffers, etc.
It
attempts
to minimize resource conflicts. The links and nodes
in
a
communication path
are
set aside dynamically
(i.e., only for the requested time
slot)
in the resource
database. If the resource reservation process is suc-
cessful, the message task is queued for scheduling.
NoC
Scheduler;
The NoC scheduler executes
the
T,’S
according to
the
particular network service require-
ments. It attempts to minimize resource occupancy.
In
a
network, resource occupation
is
dictated by the size
of the message.
4
Hand-held Multimedia Terminal
In
this section, we will demonstrate the capabilities
of
our
system-level modeling framework by presenting
the simulation results of
a
multiprocessor SoC-based mul-
timedia device which concurrently runs PEG encod-
ing/decoding,
MP3
decoding, and GSM encodingldecoding
all in real-time. Figure
2
shows the five task graphs which
are defining the core functionality of our multimedia de-
vice. The pre-processing steps for abstracting the applica-
tion code, like the extraction of the static task graph parame-
ters through code profiling, and mapping the task graphs to
the NoC architectures have been performed manually
[SI.
For
the purpose of demonstrating the capabilities of
our
modeling framework, the applications have been mapped
on four processing elements (see Figure
31,
three fast
pro-
cessors
(25
MHz),
and one slow processor
(10
MHz).
Each
of the four processors has its own local memory and all the
four processors are interconnected by a torus network.
Us-
ing distributed memory for instructions and data greatly re-
duces the traffic in the network.
JPEG Encder JPEG Decoder
MP3 Decoder
1
MP3 Decoder 2
/torus
&
GSM
EncOder GSM Decoder
Figure
3.
Multiprocessor architecture
for
the multi-
media
application.
The MP3 decoder
is
the most critical multimedia appli-
cation and mapping its task graph on
a
single processor,
even on
a
fast processor, reveals that some tasks
miss
their
deadlines. Therefore, the
MP3
application task graph has
been partitioned and mapped on two fast processors which,
as
mentioned above, are interconnected through
a
NoC. The
PEG
encoder and decoder applications are mapped to
the
same two fast processors
as
the MP3 decoder, whereas the
GSM encoder is mapped onto
a
third fast processor and the
GSM decoder is mapped on
a
slow
processor. This
map-
ping results in the exchange of communication messages
between the two fast processors over the NoC.
In order to illustrate the capabilities of
our
modeling
framework, we are using two different schedulers.
RM
scheduling is used on the two fast processors to handle
PEG and
MP3,
whereas the two GSM applications are
scheduled using EDF scheduling. Table
1
summarizes the
characteristics of the multimedia application.
5.
Conclusions
We have presented
a
system-level, system-on-chip mod-
eling framework and discussed how
our
original SoC model
has been extended to handle the effects of the on-chip in-
terconnection infrastructure, i.e., the network-on-chip. We
have demonstrated the capabilities of
our
modeling frame-
work by modeling and simulating a hand-held multime-
dia terminal application mapped on
a
heterogeneous
4-
processor SoC architecture interconnected through
a
torus
83
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Figure
2.
The five
task
graphs corresponding to the multimedia applications. From left, these
are
the JPEG Encoder, JPEG
Decoder,
MP3
Decoder, GSM Encoder and
the
GSM
Decoder.
Application Type Number
of
Tasks Deadline
Processor
Clock Frequency
JPEG Encoder
5
25hs GPPO
25MHz
JPEG Decoder
6
5hs
GPPO
25MHz
MP3 Decoder
16
25ms GPPO
25MHz
GSM Encoder
53
2oms
GPPO 25MHz
GSM
Decoder
34
2hs
GPPI
IOMHz
Scheduler
]
Rate Monotonic
Rate Monotonic
Rate Monotonic
Earliest Deadline First
Earliest Deadline First
on-chip network topology. It is worth mentioning, how-
ever, that our system-level modeling framework supports
more
sophisticated scheduling policies and
NoC
topologies.
Moreover, features like including the effects
of
the network
interface and memory
accesses
as
well as dynamic load
bd-
ancing
support can be built upon by adding
more
compo-
nents
to the existing framework components. We
are
cur-
rently extending our modeling framework to include radio
and transducer components in order
to
be able to model
wireless sensor networks, i.e.,
a
distributed system
of
SoCs.
Acknowledgements
The work presented in this
paper
has been funded by the
SoC
Mobinet Project
(IST
2000-30094).
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