A top-down hardware/software co-simulation method for embedded systems based upon a component logical bus architecture
10 Feb 1998-pp 169-175
TL;DR: A top-down hardware/software co-simulation method for embedded systems is proposed and a component logical bus architecture is introduced as an interface between software components and hardware components.
Abstract: We propose a top-down hardware/software co-simulation method for embedded systems and introduce a component logical bus architecture as an interface between software components and hardware components. Co-simulation using a component logical bus architecture is possible in the same environment from the stage at which the processor is not yet determined to the stage at which the processor is modeled in register transfer language. A model whose design is based on a component logical bus architecture is replaceable and reusable. By combining such replaceable models, it is possible to quickly realize seamless co-simulation. We further describe experimental results of our approach.
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Patent•
01 Jun 2001TL;DR: An integrated design environment (IDE) is disclosed for forming virtual embedded systems as discussed by the authors, which includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators.
Abstract: An integrated design environment (IDE) is disclosed for forming virtual embedded systems The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators A software debugger interface permits a software application to be loaded and executed on the virtual embedded system A virtual test bench may be coupled to the simulation to serve as a human-machine interface In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project IP components, such as processor cores, may be evaluated using a virtual embedded system In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system
231 citations
Patent•
24 May 2000TL;DR: In this paper, a method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the FPGA is presented.
Abstract: A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software The contents from the simulator-port layout are verified with the register contents Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents
77 citations
Patent•
20 Jan 1999
TL;DR: In this article, a storage medium has been proposed for co-simulation of a set of programming instructions defining a number of data objects and operations on the data objects for use by another set of program instructions to enable the other set of instructions to be compilable into either a version suitable for use in a hardware/software simulator, or another version without the effective calls.
Abstract: A storage medium is disclosed. The storage medium having stored on it a set of programming instructions defining a number of data objects and operations on the data objects for use by another set of programming instructions to enable the other set of programming instructions to be compilable into either a version suitable for use in a hardware/software co-simulation that effectively includes calls to hardware simulation functions that operate to generate bus cycles for a hardware simulator, or another version without the effective calls, but explicitly expressed instead, suitable for use on a targeted hardware.
18 citations
Patent•
31 May 2001TL;DR: In this paper, a hardware/software co-simulation interface receives a request from a client system for configuration data for the server state in of the HPC/SOC.
Abstract: A hardware/software co-simulation permits access to a server state from any process in the hardware/software co-simulation. In one embodiment, a co-simulation interface receives a request from a client system for configuration data for the server state in of the hardware/software co-simulation. The configuration data defines memory locations in the co-simulation from which the server state can be assembled. The interface inserts the request in the co-simulation. The co-simulation responds with the configuration information. Based on the configuration information, memory operations can be performed on the server state.
11 citations
Patent•
30 Jan 2004TL;DR: In this paper, a C-based co-verification method for hardware/software co-simulation is presented, which achieves fast simulation execution by implementing a Cbased native code simulation without degrading the accuracy of timing verification.
Abstract: A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.
10 citations
References
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TL;DR: The authors demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met.
Abstract: As system design grows increasingly complex, the use of predesigned components, such as general-purpose microprocessors can simplify synthesized hardware. While the problems in designing systems that contain processors and application-specific integrated circuit chips are not new, computer-aided synthesis of such heterogeneous or mixed systems poses unique problems. The authors demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met. System functionality is captured using the HardwareC hardware description language. The synthesis of an Ethernet-based network coprocessor is discussed as an example. >
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280 citations
Additional excerpts
...There have been numerous studies [1]-[5] on: • hardware/software partitioning, • hardware/software co-synthesis, and • hardware/software co-simulation....
[...]
01 Jun 1996
TL;DR: This tutorial describes a set of criteria that can be used to compare differing approaches to hardware/software co-design to illustrate how a wide range of approaches can be viewed within a single framework.
Abstract: Over the past several years there has been a great deal of interest in the design of mixed hardware/software systems, sometimes referred to as hardware/software co-design or hardware/software co-synthesis. However, although many new design methodologies have taken the name hardware/software co-design, they often do not seem to share much in common with one another This partly due to the fact that the problem itself has so many dimensions. This tutorial describes a set of criteria that can be used to compare differing approaches to hardware/software co-design. These criteria are used in the discussion of a number of published hardware/software co-design techniques to illustrate how a wide range of approaches can be viewed within a single framework.
61 citations
Additional excerpts
...There have been numerous studies [1]-[5] on: • hardware/software partitioning, • hardware/software co-synthesis, and • hardware/software co-simulation....
[...]
DOI•
18 Mar 1996TL;DR: In this article, an orchestrated combination of architectural strategies, parameterized libraries, and software CAD tools is presented to solve the embedded architecture co-synthesis and system integration problem.
Abstract: Embedded system architectures comprising of software programmable components (e.g. DSP, ASIP, and micro-controller cores) and customized hardware co-processors, integrated into a single cost-efficient VLSI chip, are emerging as a key solution to today's microelectronics design problems. This trend is being driven by new emerging applications in the areas of wireless communication, high-speed optical networking, and multimedia computing. A key problem confronted by embedded system designers today is the rapid prototyping of application-specific embedded system architectures where different combinations of programmable processors and hardware components must be integrated together, while ensuring that the hardware and software parts communicate correctly. In this paper, we present a solution to this embedded architecture co-synthesis and system integration problem based on an orchestrated combination of architectural strategies, parameterized libraries, and software CAD tools.
21 citations
01 Jan 1993
18 citations
"A top-down hardware/software co-sim..." refers methods in this paper
...For the instruction set model, an ASAP instruction set simulator written in C and a VPS cycle-based simulator [10] capable of high-speed execution of the hardware component RTL model were used in the single process environment....
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