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Proceedings ArticleDOI

A V-band wide locking range CMOS frequency divider

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TLDR
In this paper, a V-band wide locking range 0.18-μm CMOS frequency divider was proposed to improve the signal injection efficiency and locking range of the ILFD.
Abstract
This paper presents a V-band wide locking range 0.18-μm CMOS frequency divider. The resonator-based injection-locked frequency dividers (ILFD) inherently suffer from narrow locking range. The combination of common-node injection and direct injection is proposed to improve the signal injection efficiency and locking range. Compared to the conventional direct injection technique, the proposed technique is capable of doubling the divider’s locking range. Operated at 1.4 V, the frequency divider core consumes 2.8 mW of power. The measured free running frequency and output power of the divider are 28.17 GHz and −22.84 dBm, respectively. The locking range is 4.9 GHz around the input frequency of 56 GHz. With high operating frequency, wide locking range, and low power consumption, this work achieves the excellent figure-of-merit (FOM), which is much better than the frequency dividers implemented in the same generation CMOS process. The overall chip size is 0.77 × 0.49 mm2.

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Citations
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Journal ArticleDOI

Design of dual‐band MIMO monopole antenna with high isolation using slotted CSRR for WLAN

TL;DR: In this article, a dual-band multi-input multi-output (MIMO) antenna using slotted complementary split ring resonator (CSRR) was proposed for WLAN at 2.45 GHz and 5 GHz.
Journal ArticleDOI

Design of 24-GHz 0.8-V 1.51-mW Coupling Current-Mode Injection-Locked Frequency Divider With Wide Locking Range

TL;DR: In this article, a 0.8-V CMOS coupling current-mode injection-locked frequency divider (CCMILFD) with 19.5% locking range and a current-injection currentmode logic (CICML) frequency dividers have been designed and fabricated using 0.13mum 1p8m CMOS technology.
Journal ArticleDOI

Low-Power-Consumption Wide-Locking-Range Dual-Injection-Locked 1/2 Divider Through Simultaneous Optimization of VCO Loaded $Q$ and Current

TL;DR: In this article, a 1/2 dual-injection-locked frequency divider (dual-ILFD) with wide locking range and low power consumption is proposed, analyzed, and developed together with a divide-by-2 current-mode logic (CML) divider.
Journal ArticleDOI

Injection-Locked Frequency Divider Topology and Design Techniques for Wide Locking-Range and High-Order Division

TL;DR: An injection-locked frequency divider topology for wide locking-range and high-order division is presented and a self-injection technique is proposed that utilizes harmonic conversion and self- injection to improve phase-noise, locking- range, and input sensitivity simultaneously.
Dissertation

Spectrum monitor for cognitive radio

Siwen Liang
TL;DR: This thesis explores the requirements and design issues for the spectrum monitor receiver and explores the concept of figure of merit (FoM) to predict the performances versus power consumptions for active components over the next few years.
References
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Journal ArticleDOI

A study of injection locking and pulling in oscillators

TL;DR: In this paper, an identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction, and the behavior of phase-locked oscillators under injection pulling is also formulated.
Journal ArticleDOI

Superharmonic injection-locked frequency dividers

TL;DR: In this article, a first-order differential equation is derived for the noise dynamics of injection-locked oscillators, and a single-ended ILFD is designed in a 0.5-/spl mu/m CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power.
Journal ArticleDOI

A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider

TL;DR: An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators, which features wide locking ranges, a very low input capacitance, and highest frequency capability.
Proceedings ArticleDOI

A 19 GHz 0.5 mW 0.35 /spl mu/m CMOS frequency divider with shunt-peaking locking-range enhancement

TL;DR: In this paper, shunt-peaking is used as an approach to increase the locking range and lower the power dissipation at higher frequencies of a narrow-band injection-locked frequency divider.
Proceedings ArticleDOI

70GHz CMOS Harmonic Injection-Locked Divider

TL;DR: A 70GHz CMOS harmonic injection-locked divider (HILD) is presented, where a third-harmonic mixer is realized by a differential-voltage-driven MOSFET.
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