A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells
TL;DR: The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.
Abstract: In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.
Citations
More filters
TL;DR: In this article , the Wallace tree multiplier is used to implement the addition operation in each phase of the Wallace Tree and a high degree of gate-level parallelism is employed at the array level by executing multiple majority gates in the columns of the array.
Abstract: In-memory computing using emerging technologies such as resistive random-access memory (ReRAM) addresses the ‘von Neumann bottleneck’ and strengthens the present research impetus to overcome the memory wall. While many methods have been recently proposed to implement Boolean logic in memory, the latency of arithmetic circuits (adders and consequently multipliers) implemented as a sequence of such Boolean operations increases greatly with bit-width. Existing in-memory multipliers require $O(n^{2})$ cycles which is inefficient both in terms of latency and energy. In this work, we tackle this exorbitant latency by adopting Wallace Tree multiplier architecture and optimizing the addition operation in each phase of the Wallace Tree. Majority logic primitive was used for addition since it is better than NAND/NOR/IMPLY primitives. Furthermore, high degree of gate-level parallelism is employed at the array level by executing multiple majority gates in the columns of the array. In this manner, an in-memory multiplier of $O(n.log(n))$ latency is achieved which outperforms all reported in-memory multipliers. Furthermore, the proposed multiplier can be implemented in a regular transistor-accessed memory array without any major modifications to its peripheral circuitry and is also energy-efficient.
3 citations
DOI•
01 Mar 2016
TL;DR: A programmable folded cascode railto-rail operational amplifier with small settling time and transconductance feedback circuit is proposed that employs a 130 nm CMOS technology with 1.2 V power supply.
Abstract: Abstract—In this work a programmable folded cascode railto-rail operational amplifier (OpAmp) with small settling time and transconductance feedback circuit is proposed. It employs a 130 nm CMOS technology with 1.2 V power supply. The small settling time is required to charge an ADC within a given time frame. The OpAmp achieves a gain bandwidth of 19.95 MHz with a 70 pF load and a minimum settling time of 144 ns while consuming 0.551 mA quiescent current. It can be shown that with 130 nm technology, high performance amplifiers can be realized on very small area.
2 citations
18 Nov 2021
1 citations
07 Aug 2022
TL;DR: In this paper , the authors present a read circuit for RRAM cells based on voltage evaluation, which is able to resolve very small resistance ratios of up to 1.31 while offering multi-level capability.
Abstract: Memory integration is a key issue for emerging memory technologies. In order to properly integrate a novel memory technology, precise and reliable read circuits and concepts are necessary. But especially in emerging technologies, the electrical properties of the individual cells can vary widely, demanding additional flexibility. The presented circuit design offers a read circuit for RRAM cells based on voltage evaluation, that is able to resolve very small resistance ratios of up to 1.31 while offering multi-level capability. By changing some circuit parameters, it can be adopted to different given electrical properties.
1 citations
07 Aug 2022
TL;DR: In this article , the authors present a read circuit for RRAM cells based on voltage evaluation, which is able to resolve very small resistance ratios of up to 1.31 while offering multi-level capability.
Abstract: Memory integration is a key issue for emerging memory technologies. In order to properly integrate a novel memory technology, precise and reliable read circuits and concepts are necessary. But especially in emerging technologies, the electrical properties of the individual cells can vary widely, demanding additional flexibility. The presented circuit design offers a read circuit for RRAM cells based on voltage evaluation, that is able to resolve very small resistance ratios of up to 1.31 while offering multi-level capability. By changing some circuit parameters, it can be adopted to different given electrical properties.
1 citations
References
More filters
Book•
01 Jan 1977
TL;DR: In this article, the authors combine bipolar, CMOS and BiCMOS analog integrated circuits into a unified treatment that stresses their commonalities and highlights their differences, and provide valuable insights into the relative strengths and weaknesses of these important technologies.
Abstract: The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.
4,717 citations
TL;DR: A high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the Memristor element.
Abstract: Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.
853 citations
TL;DR: This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change randomAccess memory (PCRAM), and resistive random accessMemory (RRAM).
Abstract: This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change random access memory (PCRAM), and resistive random access memory (RRAM). Emerging NVM cell characteristics are summarized, and device-level engineering trends are discussed. Emerging NVM array architectures are introduced, including the onetransistor?one-resistor (1T1R) array and the cross-point array with selectors. Design challenges such as scaling the write current and minimizing the sneak path current in cross-point array are analyzed. Recent progress on megabit-to gigabit-level prototype chip demonstrations is summarized. Finally, the prospective applications of emerging NVM are discussed, ranging from the last-level cache to the storage-class memory in the memory hierarchy. Topics of three-dimensional (3D) integration and radiation-hard NVM are discussed. Novel applications beyond the conventional memory applications are also surveyed, including physical unclonable function for hardware security, reconfigurable routing switch for field-programmable gate array (FPGA), logic-in-memory and nonvolatile cache/register/flip-flop for nonvolatile processor, and synaptic device for neuro-inspired computing.
391 citations
TL;DR: Recent progress in the area of resistive random access memory (RRAM) technology which is considered one of the most standout emerging memory technologies owing to its high speed, low cost, enhanced storage density, potential applications in various fields, and excellent scalability is comprehensively reviewed.
Abstract: In this manuscript, recent progress in the area of resistive random access memory (RRAM) technology which is considered one of the most standout emerging memory technologies owing to its high speed, low cost, enhanced storage density, potential applications in various fields, and excellent scalability is comprehensively reviewed. First, a brief overview of the field of emerging memory technologies is provided. The material properties, resistance switching mechanism, and electrical characteristics of RRAM are discussed. Also, various issues such as endurance, retention, uniformity, and the effect of operating temperature and random telegraph noise (RTN) are elaborated. A discussion on multilevel cell (MLC) storage capability of RRAM, which is attractive for achieving increased storage density and low cost is presented. Different operation schemes to achieve reliable MLC operation along with their physical mechanisms have been provided. In addition, an elaborate description of switching methodologies and current voltage relationships for various popular RRAM models is covered in this work. The prospective applications of RRAM to various fields such as security, neuromorphic computing, and non-volatile logic systems are addressed briefly. The present review article concludes with the discussion on the challenges and future prospects of the RRAM.
379 citations
09 Oct 2012
TL;DR: An 8-Mb multi-layered cross-point resistive RAM (ReRAM) macro has been developed with 443 MB/s write throughput (64-bits parallel write per 17.2-ns cycle), which is almost twice as fast as competing methods.
Abstract: Nonvolatile memories with fast write operation at low voltage are required as storage devices to exceed flash memory performance [1–3]. We develop an 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput (64b parallel write per 17.2ns cycle), which is almost twice as fast as existing methods, using the fast-switching performance of TaO x ReRAM [4] and the following three techniques to reduce the sneak current in bipolar type cross-point cell array structure in an 0.18μm process. First, memory cell and array technologies reduce the sneak current with a newly developed bidirectional diode as a memory cell select element for the first time. Second, we use a hierarchical bitline (BL) structure for multi-layered cross-point memory with fast and stable current control. Third, we implement a multi-bit write architecture that realizes fast write operation and suppresses sneak current. This work is applicable to both high-density stand-alone and embedded memory with more stacked memory arrays and/or scaling memory cells.
314 citations