A wedge tunnel FET device for larger tunneling area and improved ON current

doi:10.1109/NANO.2015.7388763

Proceedings Article•DOI•

A wedge tunnel FET device for larger tunneling area and improved ON current

Astha Tyagi¹, Vipin Joshi¹, Shree Prakash Tiwari¹•Institutions (1)

Indian Institute of Technology, Jodhpur¹

27 Jul 2015-pp 913-915

TL;DR: In this article, a wedge-shaped structure for TFET named Wedge-TFET (WTFET) is proposed, which is a double gate structure, showing ∼3 times higher ON current compared to planar double gate TFET device working at supply voltage of 0.6 to 1.0 V.

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Abstract: In an attempt to improve ON current and current ON/OFF ratio in tunnel field-effect Transistors (TFETs), a new wedge shaped structure for TFET named Wedge-TFET (WTFET) is proposed. This proposed device is a double gate structure, showing ∼3 times higher ON current compared to planar double gate TFET device working at supply voltage of 0.6 to 1.0 V. This increase is mainly due to increase in the tunneling area. In addition to increased current, W-TFET also shows high current ON/OFF ratio of the order ∼1012. The subthreshold swing values are slightly higher for W-TFET compared to our simulated DG-TFET, however, both of them fall in the range of 40 to 50 mV/dec. The W-TFET device with higher ON current and current ON/OFF ratio and with almost same area requirement can be a potential candidate for future low voltage applications.

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Journal Article•DOI•

Hetero-gate-Dielectric Symmetric U-shaped gate tunnel FET

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Mohammad Bagher Tajally¹, Mohammad Azim Karami¹•Institutions (1)

Iran University of Science and Technology¹

01 Oct 2017-Superlattices and Microstructures

TL;DR: Heterogeneous gate dielectric is used in a nanoscale symmetric U-shaped gate tunnel FET (SUTFET), which resulted in ION, IOFF, subthreshold swing (SS), and Iambipolar enhancement as mentioned in this paper.

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13 citations

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Journal Article•DOI•

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

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Kathy Boucart, Adrian M. Ionescu¹•Institutions (1)

École Polytechnique Fédérale de Lausanne¹

25 Jun 2007-IEEE Transactions on Electron Devices

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.

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Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

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1,230 citations

"A wedge tunnel FET device for large..." refers background or methods or result in this paper

...R using nonlocal band-to-band tunneling (BTBT) model as used in [6, 16]....
[...]
...These kind of doping values has previously been reported in [6]....
[...]
...These values are slightly higher than those reported for a conventional DG-TFET device [6]....
[...]
...In order to overcome these effects in MOS based devices there is a need for alternate devices like Tunnel Field Effect Transistors (TFETs)[3-11]....
[...]
...While the results of the device were better compared to other planar TFETs like DGTFET from literature [6], or from our simulations but the current is lower when compared to some other device structures like sandwich tunnel barrier FETs (STBFET) [3]....
[...]

Proceedings Article•DOI•

FinFET scaling to 10 nm gate length

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Bin Yu¹, Leland Chang², Shibly S. Ahmed¹, Haihong Wang¹, Scott A. Bell¹, Chih-Yuh Yang¹, Cyrus E. Tabery¹, Chau M. Ho¹, Qi Xiang¹, Tsu-Jae King², Jeffrey Bokor², Chenming Hu³, Ming-Ren Lin¹, D. Kyser¹ - Show less +10 more•Institutions (3)

Advanced Micro Devices¹, University of California, Berkeley², Hodges University³

01 Jan 2002

TL;DR: In this paper, the authors report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm.

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Abstract: While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm These MOSFETs are believed to be the smallest double-gate transistors ever fabricated Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm) The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 12 V Working CMOS FinFET inverters are also demonstrated

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611 citations

"A wedge tunnel FET device for large..." refers background in this paper

...Other device structures, such as FinFET and Gate-All-Around FETs[12, 13] have been proposed to overcome the short channel effects, however, these devices have a theoretical limitation on Sub-threshold swing (SS) as 60 mV/decade, making them unsuitable for operation at lower voltages....
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Proceedings Article•DOI•

I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q

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Kailash Gopalakrishnan¹, Peter B. Griffin¹, James D. Plummer¹•Institutions (1)

Stanford University¹

08 Dec 2002

TL;DR: The I-MOS as discussed by the authors uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa.

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Abstract: One of the "fundamental" problems in the continued scaling of MOSFETs is the 60 mV/decade room temperature limit in subthreshold slope. In this paper, we report initial studies on a new kind of transistor, the I-MOS. The I-MOS uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa. Since impact-ionization is an abrupt function of the electric field (or the carrier energy), simulations show that the device has a subthreshold slope much lower than kT/q. Simulations also show that it is indeed possible to make complementary circuits with switching speeds comparable to or exceeding CMOS. Experimental results on a silicon based prototype verify the basic concept and show very steep subthreshold slopes with high speed turn-on and turn-off. Lower bandgap materials are also being investigated to reduce the value of the breakdown voltage and permit lower voltage operation.

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367 citations

"A wedge tunnel FET device for large..." refers background in this paper

...However, the values of ION are still much lower than MOSFET devices....
[...]
...However, Impactionization MOSFET require high operating voltages paving a path for TFET, which offers low SS ( 60mV/dec) and low IOFF (~ pA) simultaneously at low operating voltages, as a potential candidate for applications in nanometer regime....
[...]
...Impact-ionization MOSFET [14] and TFET are the two devices which offer very low leakage currents and can achieve SS values less than minimum SS (~ 60mV/dec) possible in MOSFETs....
[...]

Journal Article•DOI•

Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering

[...]

Krishna Kumar Bhuwalka, Joerg Schulze, Ignaz Eisele

25 Apr 2005-IEEE Transactions on Electron Devices

TL;DR: It is shown here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to Tunnel FET scaling.

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Abstract: In this paper, we look into the scaling issues of a vertical tunnel field-effect transistor (FET). The device, a gated p-i-n diode based on silicon, showed gate-controlled band-to-band tunneling from the heavily doped source to the intrinsic channel. An exponentially increasing input characteristics, perfect saturation in the output characteristics, and off-currents of the order of 1 fA//spl mu/m for sub-100-nm channel lengths were observed. Further, with a /spl delta/p/sup +/ SiGe layer at the p-source end, improvements in the device performance in terms of on-current, threshold voltage and subthreshold swing were shown, albeit trading off the off-currents which increase with Ge content x. We show here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to tunnel FET scaling. Further, with gate workfunction engineering, the tunnel FET can be tuned to achieve a high on-current as well as very low off-currents. Due to the perfect saturation in the output characteristics, the device looks good for sub-100-nm low-power analog devices.

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330 citations

"A wedge tunnel FET device for large..." refers background in this paper

...In order to overcome these effects in MOS based devices there is a need for alternate devices like Tunnel Field Effect Transistors (TFETs)[3-11]....
[...]

Proceedings Article•

Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

[...]

Kathy Boucart¹, Adrian M. Ionescu¹•Institutions (1)

École Polytechnique Fédérale de Lausanne¹

01 Jan 2007

TL;DR: In this article, the length scaling of the double gate tunnel field effect transistor (DG tunnel FET) is studied. And the authors demonstrate that while some improvements are observed, the length scale does not dramatically affect switch figures of merit such as subthreshold slope, Ion and I off, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET.

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Abstract: In this paper, the length scaling of the silicon Double Gate Tunnel Field Effect Transistor (DG Tunnel FET) is studied. It is found that scaling limits are reached sooner by Tunnel FETs with an SiO 2 gate dielectric, while those with a high-K dielectric can be scaled further before threshold voltage, and average and point subthreshold swing are affected. It is demonstrated that the scaling of the high-K Tunnel FET is completely different than that of conventional MOS transistors. An outstanding feature of the Tunnel FET switch is that length scaling has a much weaker impact on device characteristics than does gate control (e.g. the use of a high-K dielectric), which primarily dictates the tunneling barrier width and consequently, device conduction. This paper demonstrates that while some improvements are observed, the length scaling does not dramatically affect switch figures of merit such as subthreshold slope, Ion and I off down to about 20 nm, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET. A discussion of the length dependence of the transconductance, g m , and output conductance, g ds of the Tunnel FET is presented for the first time.

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277 citations

"A wedge tunnel FET device for large..." refers background or methods or result in this paper

...R using nonlocal band-to-band tunneling (BTBT) model as used in [6, 16]....
[...]
...These kind of doping values has previously been reported in [6]....
[...]
...These values are slightly higher than those reported for a conventional DG-TFET device [6]....
[...]
...In order to overcome these effects in MOS based devices there is a need for alternate devices like Tunnel Field Effect Transistors (TFETs)[3-11]....
[...]
...While the results of the device were better compared to other planar TFETs like DGTFET from literature [6], or from our simulations but the current is lower when compared to some other device structures like sandwich tunnel barrier FETs (STBFET) [3]....
[...]

A wedge tunnel FET device for larger tunneling area and improved ON current

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"A wedge tunnel FET device for large..." refers background or methods or result in this paper

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