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Journal ArticleDOI

A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer

TL;DR: A novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion and is designed for practical applications.
Abstract: Wide-range level shifters play critical roles in ultra- low-voltage circuits and systems. Although state-of-the-art level shifters can convert a subthreshold voltage to the standard supply voltage, they may have limited operating ranges, which restrict the flexibility of dynamic voltage scaling. Therefore, this paper presents a novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion. The proposed level shifter is a hybrid structure comprising a modified Wilson current mirror and generic CMOS logic gates. The simulation and measurement results were verified using a 65-nm technology. The minimal operating voltage of the proposed level shifter was less than 200 mV based on the measurement results. In addition to the operating range, the delay, power consumption, and duty cycle of the proposed level shifter were designed for practical applications.
Citations
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Journal ArticleDOI
TL;DR: A novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage with good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations is presented.
Abstract: This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 μm show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3×, 19×, 29× respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.

82 citations


Cites methods from "A Wide-Range Level Shifter Using a ..."

  • ...To address this issue, several modified Type II level shifter have been proposed [18]–[20]....

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  • ...In [20] a level shifter with a modified Wilson current mirror hybrid buffer is proposed....

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Journal ArticleDOI
TL;DR: An energy-efficient level shifter able to convert extremely low level input voltages to the nominal voltage domain based on the single-stage differential-cascode-voltage-switch scheme that exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption.
Abstract: This brief presents an energy-efficient level shifter (LS) able to convert extremely low level input voltages to the nominal voltage domain. To obtain low static power consumption, the proposed architecture is based on the single-stage differential-cascode-voltage-switch scheme. Moreover, it exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption, while a split input inverting buffer is used as the output stage to further improve energy efficiency. When implemented in a commercial 180-nm CMOS process, the proposed design can up-convert from the deep subthreshold regime (sub-100 mV) to the nominal supply voltage (1.8 V). For the target voltage level conversion from 0.4 to 1.8 V, our LS exhibits an average propagation delay of 31.7 ns, an average static power of less than 60 pW, and an energy per transition of 173 fJ, as experimentally measured across the test chips.

73 citations


Cites background or methods from "A Wide-Range Level Shifter Using a ..."

  • ...Among the LSs realized in the 0.18-μm technology node, the one presented in [4] results to be the most energy hungry....

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  • ...However, as specified in Section II, the two most recent LSs [11], [12] were replicated in the adopted 0.18-μm CMOS process....

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  • ...The single-stage DCVS-based LSs presented in [8] and in [12] use diode-connected transistors to limit current contention at the critical discharging internal nodes during the output switching....

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  • ...Differently from current mirror configurations, LSs based on differential cascode voltage switch (DCVS) structure have close-to-zero standby power consumption due to the presence of complementary pull-up networks (PUNs) and pull-down networks (PDNs)....

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  • ...To manage static power issues, some modified Wilson current mirror-based LS circuits were recently presented in [11] and [14]....

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Journal ArticleDOI
TL;DR: The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures and stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations.
Abstract: In the applications of biometric authentication and video surveillance, the image sensor is expected to provide certain degree of trust and resiliency. This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that involves image sensor as a trusted entity. The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures. The proposed differential readout stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations. The threshold of difference can be tightened to winnow out more unstable response bits from the challenge-response space offered by modern image sensors to enhance the reliability under harsher operating conditions and loosened to improve its resiliency against masquerade attacks in routine operating environment. The proposed design can be classified as a weak PUF which is resilient to modeling attacks, with direct access to its challenge-response pair restricted by the linear feedback shift register. Our experiments on the reset voltages extracted from a 64 $\times$ 64 image sensor fabricated in 180 nm 3.3 V CMOS technology demonstrated that robust and reliable challenge-response pairs can be generated with a uniqueness of 49.37% and a reliability of 99.80% under temperature variations of $15\sim 115~^{\circ}{\rm C}$ and supply voltage variations of $3\sim 3.6\ {\rm V}$ .

71 citations

Journal ArticleDOI
TL;DR: In this article, a mixed TFET-MOSFET level shifter (LS) for voltage up-conversion from the ultralow-voltage regime is proposed.
Abstract: In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET–MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET–MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET–MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions.

63 citations


Cites background or methods from "A Wide-Range Level Shifter Using a ..."

  • ...Four of the most recent and efficient LS designs [18]–[21] were considered as case study....

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  • ...Within this context, several level shifter (LS) circuit topologies were recently proposed for speed- and energy-efficient wide-range conversion from the deep subthreshold regime up to the nominal supply voltage level [16]–[21]....

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  • ...Mixed TFET–MOSFET LS design version of circuits reported in (a) [18], (b) [19], (c) [20], and (d) [21]....

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  • ...Finally, the circuit proposed in [21] [shown in Fig....

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Journal ArticleDOI
TL;DR: This brief introduces a novel LS circuit with NMOS-diode-based current limiter for current contention reduction to achieve robust and efficient level conversion and explores the inverse narrow width effect to increase the drivability of the pull-down devices for delay reduction.
Abstract: Level shifters (LS) are crucial interface circuits for multisupply voltage designs, and it is challenging to achieve both robust and efficient level conversion from subthreshold to aforementioned threshold. In this brief, we propose two circuit techniques for a novel subthreshold LS with wide conversion range. First, we introduce a novel LS circuit with NMOS-diode-based current limiter for current contention reduction to achieve robust and efficient level conversion. Second, we explore the inverse narrow width effect to increase the drivability of the pull-down devices for delay reduction. When implemented in a commercial 65-nm MTCMOS process, the proposed LS achieves robust conversion from deep subthreshold (sub-100 mV) to nominal supply voltage (1.2 V). For the target conversion from 0.3 to 1.2 V, the proposed LS shows on average 25.1-ns propagation delay, 30.7-fJ energy efficiency, and 2.5-nW leakage power across 25 test chips.

59 citations

References
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Journal ArticleDOI
22 Jan 2010
TL;DR: This paper explores how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point, and introduces a pass-transistor based logic family that excels in this operational region.
Abstract: Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

391 citations

Journal ArticleDOI
TL;DR: It is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect and common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.
Abstract: In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is accompanied by rigorous analysis for each key concept. The analysis ranges from the circuit to the micro-architectural level, and reference is given to process, physical and system levels when necessary. Among the main goals of this paper, it is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect. Accordingly, common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.

363 citations


"A Wide-Range Level Shifter Using a ..." refers methods in this paper

  • ...D YNAMIC VOLTAGE SCALING (DVS) has been widely used in digital processing elements for reducing energy consumption, and aggressive voltage scaling has extended the voltage range into the subthreshold region [1]....

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Journal ArticleDOI
TL;DR: This SoC is designed so the integration and interaction of circuit blocks accomplish an integrated, flexible, and reconfigurable wireless BSN SoC capable of autonomous power management and operation from harvested power, thus prolonging the node lifetime indefinitely.
Abstract: This paper presents an ultra-low power batteryless energy harvesting body sensor node (BSN) SoC fabricated in a commercial 130 nm CMOS technology capable of acquiring, processing, and transmitting electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG) data. This SoC utilizes recent advances in energy harvesting, dynamic power management, low voltage boost circuits, bio-signal front-ends, subthreshold processing, and RF transmitter circuit topologies. The SoC is designed so the integration and interaction of circuit blocks accomplish an integrated, flexible, and reconfigurable wireless BSN SoC capable of autonomous power management and operation from harvested power, thus prolonging the node lifetime indefinitely. The chip performs ECG heart rate extraction and atrial fibrillation detection while only consuming 19 μW, running solely on harvested energy. This chip is the first wireless BSN powered solely from a thermoelectric harvester and/or RF power and has lower power, lower minimum supply voltage (30 mV), and more complete system integration than previously reported wireless BSN SoCs.

311 citations

Journal ArticleDOI
TL;DR: A novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels and does not require a static current flow and can therefore offer considerable static power savings is proposed.
Abstract: In this brief, we propose a novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels. In contrast to other existing implementations, it does not require a static current flow and can therefore offer considerable static power savings. The circuit has been optimized and simulated in a 90-nm process technology. It operates correctly across process corners for supply voltages from 100 mV to 1 V on the low-voltage side. At the target design voltage of 200 mV, the level shifter has a propagation delay of 18.4 ns and a static power dissipation of 6.6 nW. For a 1-MHz input signal, the total energy per transition is 93.9 fJ. Simulation results are compared to an existing subthreshold to above-threshold level shifter implementation from the paper of Chen et al.

163 citations


"A Wide-Range Level Shifter Using a ..." refers background in this paper

  • ...(a) a cross-coupled (CC) structure; (b) a current mirror (CM); (c) a Wilson current mirror (WCM) [7]; (d) a two-stage cross-coupled structure (TSCC) [8]; (e) cross-coupled NOR gates and part of a NOR gate (CCPNR) [6]; (f) a logic error correction circuit (LECC) [9]....

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  • ...When VDD1 is subthreshold and VDD2 is high, the MWCM structure balances the rising and falling delay at Node A, without losing the original static bias that is favored in the WCM LS [7]....

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Journal ArticleDOI
TL;DR: This brief presents a fast energy-efficient level converter capable of converting an input signal from subthreshold voltages up to the nominal supply voltage with robust results from a 130-nm test chip.
Abstract: This brief presents a fast energy-efficient level converter capable of converting an input signal from subthreshold voltages up to the nominal supply voltage. Measured results from a 130-nm test chip show robust conversion from 188 mV to 1.2 V with no intermediate supplies required. A combination of circuit methods makes the converter robust to the large variations in the current characteristics of subthreshold circuits. To support dynamic voltage scaling, the level converter can upconvert an input at any voltage within this range to 1.2 V.

123 citations


"A Wide-Range Level Shifter Using a ..." refers background in this paper

  • ...The single-Vt TSCC LS has a moderate speed restricted to some VIN-VOUT combinations because the NMOS header reduces the circuit speed....

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  • ...For example, the TSCC LS is a dual-Vt design, but some subthreshold LSs may use triple-Vt transistors [10], [11], and other LSs use thick oxide and zero-Vt transistors [16], [17]....

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  • ...header NMOS, which expands the convertible input voltage [8]....

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  • ...However, because this work focused on LS structure and used single-Vt transistors, only the TSCC LS was involved and adapted to a single-Vt version for comparison....

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  • ...1(d) shows a two-stage CC LS (TSCC), of which the pull-up driving strength is reduced by a header NMOS, which expands the convertible input voltage [8]....

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