About Regularity of Collections of Sets
Summary (3 min read)
Introduction
- Three dimensional (3D) system integration is a highly promising ‘more-than-Moore’ technology that facilitates high density integration by extending planar ICs vertically.
- This results in TSV-based 3D integration incurring high design and manufacturing costs [2].
- To address this, recent research has explored the use of inductive coupling links (ICLs) to transmit data between vertically stacked dies.
- This inflates the cost and complexity of devices, and the addition of wire bonds undermines many of the benefits associated with contactless integration.
- In achieving this, the novel contributions of this paper can be summarised as follows: A bi-phase shift-keying ICL transceiver architecture that achieves vertical data and power delivery concurrently within a 3D-IC.
II. BACKGROUND
- Contactless 3D integration, most notably using near-field inductive coupling to communicate data, has been proposed as a low-cost alternative to TSVs for designing 3D-ICs [2].
- In such systems, data is encoded in a series of current pulses which are fed through a planar transmit (TX) inductor, fabricated in the upper BEOL interconnect layers of the transmitting die.
- Because of this, 3D-ICs using ICLs often achieve power delivery through other separate means, the most common being wire-bonding.
- HDSVs are vertical channels formed from highly doped wells to deliver power through dies after aggressive thinning.
- Another method of transferring power between vertically stacked dies is using wireless power transfer (WPT).
III. CONCURRENT POWER AND DATA DELIVERY ARCHITECTURE
- To address this challenge, as discussed in the introduction, the aim of the CoDAPT architecture is to facilitate power and data delivery concurrently using a single inductive channel.
- To achieve this, continuous bi-phase shift keying (BPSK) modulation will be used to ensure constant power delivery between tiers, irrespective of the TX data stream (unlike prior works which discretise transmission).
- The entire system is designed for on-chip integration and will hence facilitate straightforward, low-cost 3D integration where dies can be fabricated, and then stacked, with no additional processing required.
- The design of each element is documented below.
A. Bi-Phase Transceiver Design
- Fig. 3 illustrates the BPSK modulation scheme proposed for use in this work.
- The operation of this circuit is illustrated in the dashed circles in Fig.
- The differential pair will pull LATCH N high, and hence a ‘0’ will be received.
- Because of this, a trade-off between power delivery and power efficiency exists within the transceiver:.
- To select an inductor layout for use in CoDAPT, the pareto frontier was added to Fig. 8 and an arbitrary minimum bandwidth of 1GHz was defined, to remain competitive with prior ICL data links [6].
C. Tuning Circuit Design
- The resistance R and capacitance C of the coil may only be selected from a finite number of RC combinations that correspond to real, physical inductors.
- Because of this, the performance of the system can be ‘fine-tuned’ by adding a series-parallel tuning circuit before and after the coil, as shown in Fig.
- In order to ensure maximal power delivery between tiers within the 3D-IC, the link should operate at resonance [9].
- Resonant operation also ensures that the received voltages are sufficient to allow direct LDO regulation (to the nominal 1.2V) without requiring an additional boost converter.
- No alteration is made to the resistance, however a small tuning capacitor C is added in parallel with the coil, as shown on Fig. 2, to achieve resonance at 2GHz.
D. Rectifier and Low Drop-Out Regulator Design
- To rectify the received BPSK signal (and hence recover the transmitted power), a CMOS cross-coupled rectifier is used as illustrated in Fig. 9 (a).
- Work by Han et al. [9] presents extensive comparison of available on-chip rectifier solutions for this style of application, concluding that a cross-coupled rectifier can provide the highest efficiency [9].
- Following this rectification stage, a low-drop-out regulator is incorporated in order to regulate the power supply in the recipient die.
- The regulator operates on the principal that as the voltage rises, the comparator stage (2) (that compares to the band-gap reference, BG REF) will cause the gate voltage of MP16 to increase, hence increasing the resistance across it.
- The size of the storage buffer (placed at the output, Vsupply) for experiments in this paper was selected to be 1pF.
A. Experimental Set-Up
- Combining each of these components, the proposed architecture was experimentally validated using commercial simulation tools.
- The layout was imported to Ansys HFSS for EM simulation of the channel, using the stack-up in Fig. 10.
- Here, the default metal (and corresponding dielectric) layer thicknesses associated with the TSMC 65nm technology are used (passivation = 2 μm, metal = 0.9 μm) and the epoxy thickness is assumed to be 2 μm.
- The only additional processing assumed is wafer thinning to 50 μm, in-line with realistic fabrication capabilities.
- Results from these simulations are presented below.
B. Results
- Initially, the start-up behaviour of the CoDAPT system was assessed, also known as 1) Start-Up.
- Fig. 11 shows the transient performance of the proposed system during this time.
- Here, a current sink of 0.5mA (representing extraneous circuits in the recipient die) is applied.
- After the warm-up period has elapsed, this transceiver was found to exhibit a maximum bandwidth of 1.3Gbps, slightly larger than the theoretical maximum suggested on Fig.
- To ascertain the silicon footprint of the approach, physical layout of the CoDAPT transceiver was 2Quoted figures are inclusive of the CoDAPT circuitry power dissipation (including data recovery) and carrier signal generation.
C. Advantages of the CoDAPT Approach
- As discussed in the introduction, CoDAPT enables ultralow cost 3D integration, where no additional processing is required due to the fact that both power and data are delivered wirelessly.
- Previously, fully wireless 3D integration could only be realised using combinations of WPT schemes and data ICLs, resulting in significant area overhead.
- 1) Comparison With Existing Work: Fig. 12 (a) compares the power delivery efficiency of the proposed approach against other works exploring WPT between stacked dies.
- Modelling each CPU as an Arm M0+ MCU results in a power delivery requirement of approximately 3.0mW [16] alongside the data bandwidth requirement of 3.2Gbps.
- From the figure, it can be observed that CoDAPT outperforms each approach in terms of area efficiency, by at least 1.7× through concurrent data and power transmission, demonstrating that CoDAPT is successful in achieving its aim.
D. Tolerance to Lateral Misalignment
- Finally, this sub-section evaluates the performance CoDAPT when misalignment exists between stacked tiers.
- Fig. 14 illustrates the influence of lateral die-to-die misalignment on the coupling coefficient, k (c.f. Fig. 6).
- Fig. 15 translates these k values into power delivery performance values, expressed as a percentage of the average perfectly-aligned case (0.83mW).
- Setting a target performance tolerance of ±10%, results show that the proposed design allows ± 28 μm of lateral misalignment in x and y directions (equating to a total offset of 39.6 μm, almost half of the coil’s radius) whilst remaining within this target.
- When compared to the use of TSVs, this represents an order-of-magnitude improvement, as TSVs typically demand sub-micron alignment accuracy [17].
V. CONCLUSIONS
- This paper presents a novel fully wireless ICL transceiver , for 3D integration, where data and power can be concurrently delivered through a single channel.
- Thorough evaluation demonstrated that CoDAPT achieves a data-rate of 1.3Gbps (BER< 10−9) whilst simultaneously transferring 0.83mW of power per channel under typical operating conditions.
- For the integration scenario discussed in this paper, the area savings when using CoDAPT were in excess of 1.7× compared to the state-of-the-art.
- Results also demonstrate tolerance of ±28 μm lateral die-to-die stacking misalignment, representing an important progression towards low-cost fully wireless 3D integration.
Did you find this useful? Give us your feedback
Citations
1,282 citations
253 citations
Cites background or methods from "About Regularity of Collections of ..."
...An important theme in computational mathematics is the relationship between “conditioning” of a problem instance and speed of convergence of iterative solution algorithms on that instance....
[...]
...Here we show, in complete generality, that this method converges locally to a point in the intersection of the sets, at a linear rate governed by an associated regularity modulus....
[...]
...We mention some nonconvex examples below....
[...]
180 citations
110 citations
Cites background from "About Regularity of Collections of ..."
...[18] Thorough discussions can be found in [18,19] and the references therein....
[...]
105 citations
References
3,283 citations
2,202 citations
"About Regularity of Collections of ..." refers background in this paper
...[25,31]) to themetric (or pseudo) regularity property [11,12] (and to the Aubin property[1, 31] of the inverse mapping)....
[...]
1,540 citations
1,528 citations
Related Papers (5)
Frequently Asked Questions (8)
Q2. What are the main characteristics of a collection of sets?
Regularity properties of collections of sets play an important role in different fields of optimization and approximation: constraint qualifications, error bounds, convergence analysis, etc. (see [3,7,26] for numerous examples).
Q3. what is the definition of weak sharp minima?
Weak sharp minimaSimilar to error bounds a close optimization theory concept of weak sharp minima (see [6–8,29]) can be related to the regularity of collections of sets.
Q4. what is the simplest way to find a weakened version of f?
Then there exists an α > 0 and a δ > 0 such that for any ρ ∈ (0,δ ], x ∈ x◦ + δB with F(x) ∈C∩ (y◦+δB) one can find(i) a u1 ∈ x+ρB such thatFi(u1)≤ Fi(x)−αρ, i = 1,2, . . . ,m, Fi(u1) = 0, i = m+1, . . . ,n,(ii) a u2 ∈ x+ρB such thatFi(u2)≥ Fi(x)+αρ, i = 1,2, . . . ,m, |Fi(u2)| ≥ αρ, i = m+1, . . . ,n.Certainly it can make sense to consider a weakened version of Proposition 16 if to assume strong regularity not of the “whole” of F , but of the mapping consisting only of those components which correspond to equalities and active inequalities.
Q5. What was the definition of extremality for a collection of sets?
The local optimality of x◦ is then equivalent to the condition Ω1∩ int Ω2∩ (x◦+ρB) = /0 for some ρ > 0.The concept of extremality for a collection of sets was first defined in [21].
Q6. What is the purpose of this paper?
This paper continues investigations of stationarity and regularity properties of collections of sets in normed spaces started in [19].
Q7. What is the general definition of the collection of sets?
The (strong) regularity of the collection of sets is a natural counterpart of the (weak) stationarity property and can be used e.g. when formulating constraint qualifications in mathematical programming.
Q8. What is the general generality of the strong regularity property?
Note that (local) linear regularity is in general weaker than the strong regularity property considered here (see the example at the end of subsection 3.3).