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Proceedings ArticleDOI

Abstract RTOS modeling for multiprocessor system-on-chip

19 Nov 2003-pp 147-150
TL;DR: A modeling framework consisting of basic RTOS service models; scheduling, synchronization, and resource allocation, and a generic task model that is able to model periodic and aperiodic tasks as well as task properties such as varying execution times, offsets, deadlines, and data dependencies is proposed.
Abstract: In this paper, we present a SystemC-based framework to study the effects of running multi-threaded application software on a multiprocessor platform under the control of one or more abstract real-time operating systems (RTOS's). We propose a modeling framework consisting of basic RTOS service models; scheduling, synchronization, and resource allocation, and a generic task model that is able to model periodic and aperiodic tasks as well as task properties such as varying execution times, offsets, deadlines, and data dependencies. A given multiprocessor system is formed by the composition of RTOS service models and the allocation of tasks (the application software) onto RTOS's. We demonstrate the potential of our approach by simulating and analyzing a small multiprocessor system.
Citations
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Journal ArticleDOI
TL;DR: Techniques are proposed to accurately model the detailed RTOS functionality on top of the SystemC execution kernel, which allows timed-simulation and refinement of the RT/E SW code in SystemC.
Abstract: SystemC is committed to support the requirements for an integrated, HW/SW co-design flow, thus allowing the development of complex, multiprocessing, Systems-on Chip (MpSoC). To make this possible, efficient modeling and simulation methodologies for Real-Time, Embedded (RT/E) SW in SystemC have to be developed, so that the designer can verify and refine the application SW together with the rest of the elements of the platform. Accurate modeling of the application SW requires an accurate model of the RTOS. Nevertheless, low-level, dynamic timing characteristics of the RTOS such as time-slicing, priority-based preemptive scheduling, interrupts and exceptions do not have a direct implementation in SystemC. In this paper, techniques are proposed to accurately model the detailed RTOS functionality on top of the SystemC execution kernel. The model allows timed-simulation and refinement of the RT/E SW code in SystemC. The simulation technology has been applied to the development of a high-level, POSIX simulation library in SystemC. The library allows the designer a fast, sufficiently accurate, timed simulation of the application SW running on top of POSIX. As most current RTOSs support this standard, the library is portable to different development frameworks. The library provides the required infrastructure for a complete, multiprocessing, HW/SW co-simulation environment at different abstraction levels using SystemC.

63 citations


Cites methods from "Abstract RTOS modeling for multipro..."

  • ...The system is conceived as a collection of tasks and the model allows analysis of the effect of a certain scheduling policy. The functionality is not exercised [ 19 ]....

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Proceedings ArticleDOI
19 Jan 2009
TL;DR: The proposed “cross-annotation” technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level, and takes into account the processor-specific optimizations at the compiler level.
Abstract: We propose an automatic instrumentation method for embedded software annotation to enable performance modeling in high level hardware/software co-simulation environments. The proposed "cross-annotation" technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level. Thus, target and annotated native binaries are guaranteed to have isomorphic control flow graphs (CFG). The proposed method takes into account the processor-specific optimizations at the compiler level and proves to be accurate with low simulation overhead.

54 citations


Cites methods from "Abstract RTOS modeling for multipro..."

  • ...In [7], the authors adopt a different approach by requiring the designer to specify the overall WCET of a software task making their approach suitable for the analysis of system real-time properties but not for performance modeling....

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Proceedings ArticleDOI
10 Mar 2008
TL;DR: This paper eliminates the granularity dependency by applying the Result Oriented Modeling (ROM) technique previously used only for communication modeling, which allows precise preemptive scheduling, while retaining all the benefits of abstract RTOS modeling.
Abstract: With the increasing SW content of modern SoC designs, modeling and development of Hardware Dependent Software (HDS) become critical. Previous work addressed this by introducing abstract RTOS modeling [6], which exposes dynamic scheduling effects early in the system design flow. However, such models insufficiently capture preemption. In particular, the accuracy of preemption depends on the granularity of the timing annotation. For an accurately modeled interrupt response time, very fine-grained timing annotation is necessary, which contradicts the RTOS abstraction idea and is detrimental to simulation performance.In this paper, we eliminate the granularity dependency by applying the Result Oriented Modeling (ROM) technique previously used only for communication modeling. Our ROM approach allows precise preemptive scheduling, while retaining all the benefits of abstract RTOS modeling. Our experimental results demonstrate tremendous improvements. While the traditional model simulated an interrupt response time with a severe inaccuracy (12x longer in average and 40x longer for 96th percentile), our ROM-based model was accurate within 8% (average and 50th percentile) using identical timing annotations.

49 citations

Proceedings ArticleDOI
03 Dec 2003
TL;DR: A NoC model is presented which, together with a multiprocessor real-time operating system (RTOS) model, allows us to model and analyze the behavior of a complex system that has a real- time application running on a multip rocessor platform.
Abstract: With the increasing number of transistors available on a single chip, the system-on-chip (SoC) paradigm has evolved to exploit its full potential. As many processors can be accommodated on a single chip, this paradigm has forced a communication-centric, as opposed to a computation-centric, design view. Thus, the choice, management and modeling of the SoC interconnect is essential for an accurate evaluation and optimization of the global performance of a system. Recently, the notion of network-on-chip (NoC) has been introduced as a way to extend the classical bus-based interconnection, which is still the dominant interconnect structure for SoCs, into a dedicated, segmented and, possibly, packet-switched network fabric (Benini et al., 2002). In this paper, we present a NoC model which, together with a multiprocessor real-time operating system (RTOS) model, allows us to model and analyze the behavior of a complex system that has a real-time application running on a multiprocessor platform. We demonstrate the potential of our model by simulating and analyzing a small multiprocessor system connected through different NoC topologies, and discuss how the simulation model may be used during the design-space exploration phase.

43 citations


Cites background or methods from "Abstract RTOS modeling for multipro..."

  • ...[8, 12, 16, 17, 18, 19] further explain allocation, scheduling and synchronization in RTOS’s....

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  • ...For details on the model and how it is implemented in SystemC (including the use of the Master-Slave library), we refer to [9] and [16]....

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  • ...We extend our previous work [9, 16] on the modeling of a multi-threaded application, running on a multiprocessor platform under the control of one or more abstract RTOS’s, with a model of an on-chip network which can provide provisions for run-time inspection and observation of the onchip communication....

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  • ...Using this approach, we have demonstrated that our, previously proposed [9, 16], abstract RTOS model can be extended to include an abstract NoC processor that can effectively model the system-level effects of any NoC architecture....

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Journal ArticleDOI
TL;DR: An abstract system-level modelling and simulation framework (ARTS) which allows for cross-layer modelling and analysis covering the application layer, middleware layer, and hardware layer for MPSoC designers to explore and analyze the network performance under different traffic and load conditions.
Abstract: One of the challenges of designing a heterogeneous multiprocessor SoC is to find the right partitioning of the application for the target platform architecture. The right partitioning is dependent on the characteristics of the processors and the network connecting them as well as the application. We present an abstract system-level modelling and simulation framework (ARTS) which allows for cross-layer modelling and analysis covering the application layer, middleware layer, and hardware layer. ARTS allows MPSoC designers to explore and analyze the network performance under different traffic and load conditions, consequences of different task mappings to processors (software or hardware) including memory and power usage, and effects of RTOS selection, including scheduling, synchronization and resource allocation policies. We present the application and platform models of ARTS as well as their implementation in SystemC. We present the usage of the ARTS framework as seen from platform developers' point of view, where new components may be created and integrated into the framework, and from application designers' point of view, where existing components are used to explore possible implementations. The latter is illustrated through a case study of a real-time, smart phone application consisting of 5 applications with a total of 114 tasks mapped onto different platforms. Finally, we discuss the simulation performance of the ARTS framework in relation to scalability.

37 citations


Cites methods from "Abstract RTOS modeling for multipro..."

  • ...Previously, in [17, 19] and [18], we have introduced some of the components of the ARTS framework....

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References
More filters
Journal ArticleDOI
TL;DR: An investigation is conducted of two protocols belonging to the priority inheritance protocols class; the two are called the basic priority inheritance protocol and the priority ceiling protocol, both of which solve the uncontrolled priority inversion problem.
Abstract: An investigation is conducted of two protocols belonging to the priority inheritance protocols class; the two are called the basic priority inheritance protocol and the priority ceiling protocol. Both protocols solve the uncontrolled priority inversion problem. The priority ceiling protocol solves this uncontrolled priority inversion problem particularly well; it reduces the worst-case task-blocking time to at most the duration of execution of a single critical section of a lower-priority task. This protocol also prevents the formation of deadlocks. Sufficient conditions under which a set of periodic tasks using this protocol may be scheduled is derived. >

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Proceedings ArticleDOI
01 Jun 2000
TL;DR: A system-level design environment, aimed at System-on-Chip (SOC) designs, including real-time embedded software, is proposed, observing that embedded software makes SOC designs essentially dynamic, and so a SOC modeling environment must include dynamic behavior.
Abstract: In this paper we propose a system-level design environment, aimed at System-on-Chip (SOC) designs, including real-time embedded software. While many SOC modeling languages originate from hardware description languages, and thus tend to describe statical architectures, we observe that embedded software makes SOC designs essentially dynamic, and so a SOC modeling environment must include dynamic behavior. Such behavior is analogous to the services an Operating System offers in the software world, hence the term System-on-Chip Operating System (SoCOS).

87 citations

Journal ArticleDOI
29 Jan 2003
TL;DR: An instance of the methodology developed in the TAXYS project for the modeling and analysis of real-time systems programmed in the Esterel language is shown, by using pragmas, time constraints characterizing the execution platform and the external environment.
Abstract: We present a methodology for building timed models of real-time systems by adding time constraints to their application software. The applied constraints take into account execution times of atomic statements, the behavior of the system's external environment, and scheduling policies. The timed models of the application obtained in this manner can be analyzed by using time analysis techniques to check relevant real-time properties. We show an instance of the methodology developed in the TAXYS project for the modeling and analysis of real-time systems programmed in the Esterel language. This language has been extended to describe, by using pragmas, time constraints characterizing the execution platform and the external environment. An analyzable timed model of the real-time system is produced by composing instrumented C-code generated by the compiler. The latter has been re-engineered in order to take into account the pragmas. Finally, we report on applications of TAXYS to several nontrivial examples.

60 citations

Book ChapterDOI
08 Oct 2001
TL;DR: The evolution of information sciences and technologies is characterized by the extensive integration of embedded components in systems used in various application areas, from telecommunications to automotive, manufacturing, medical applications, e-commerce etc.
Abstract: The evolution of information sciences and technologies is characterized by the extensive integration of embedded components in systems used in various application areas, from telecommunications to automotive, manufacturing, medical applications, e-commerce etc. In most cases, embedded components are real-time systems that continuously interact with other systems and the physical world. Integration and continuous interaction of software and hardware components makes the assurance of global quality a major issue in system design. The failure of a component may have catastrophic consequences on systems performance, security, safety, availability etc.

55 citations

Proceedings ArticleDOI
03 Mar 2003
TL;DR: This paper evaluates a high-level, layered software-on-hardware performance modeling environment called MESH that captures coarse-grained, interacting system elements and shows that both high and low level models converge on the same architecture when design modifications are classified as good or bad performance impacts.
Abstract: A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detailed design. This paper evaluates a high-level, layered software-on-hardware performance modeling environment called MESH that captures coarse-grained, interacting system elements. The validity of the high-level model is established by comparing the outcome of the high-level model with a corresponding low-level, cycle-accurate instruction set simulator. We model a network processor and show that both high and low level models converge on the same architecture when design modifications are classified as good or bad performance impacts.

36 citations